daver2
10k Member
Marty,
The logic you are looking for is in a little block called EAGEN. If you look at the schematic just to the right of the MBOUT connector you should see an EAGEN block followed by the AMUX block followed by the ALU block. If you start LOGISIM and double-click in the middle of these little blocks (with the simulation hand selected in LOGISIM) then the little block should open up to reveal the logic that it contains.
In response to your edit: Yes, I cheated. This bit of logic came from my microcoded PDP-8 - so I knew it worked. There is nothing wrong with the original NAND and INVERTER implementation though (although there are three packages there and only two for the MUX solution - but I bet some of the spare gates from the second NAND and the INVERTER package are used elsewhere meaning you can't just swap them for two MUX packages).
Dave
The logic you are looking for is in a little block called EAGEN. If you look at the schematic just to the right of the MBOUT connector you should see an EAGEN block followed by the AMUX block followed by the ALU block. If you start LOGISIM and double-click in the middle of these little blocks (with the simulation hand selected in LOGISIM) then the little block should open up to reveal the logic that it contains.
In response to your edit: Yes, I cheated. This bit of logic came from my microcoded PDP-8 - so I knew it worked. There is nothing wrong with the original NAND and INVERTER implementation though (although there are three packages there and only two for the MUX solution - but I bet some of the spare gates from the second NAND and the INVERTER package are used elsewhere meaning you can't just swap them for two MUX packages).
Dave
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