Recent content by MattisLind

I am not sure what you want to do. But if you want to have another branch it as simple as do a git checkout -b <new branch>. Then put your files there and commit changes and push the new branch. You need to do a git push --set-upstream origin <new branch>. In the Github GUI you can then select...

Are you certain that the ROM address counter is reset when reading the ROM Data register? I.e have you written to the ROM address register in order to reset the counter? I don't think the HDD nor the floppy controller had a Diag ROM as the DECNA has. They only have one single word that is the...

Most likely not unibus. Just hex size,and for some reason they kept the contact fingers. The fingers aren’t even gold-plated. Maybe for testing purposes?

Looks like a really nice disassembler! Is it a windows program?

I have a VT55 that I need to spend some time on. Do you have the schematic for the ”graphics” board?

I found this in the tech manual: So XACKAL is also connected to the BRPLYL circuit, not just the latch. I don't think you need to trace it.

Thanks! I wonder how the BRPLYL signal is generated on the CTI bus. Surely a ACK / READY signal from the 8207 has to be involved somehow. A CTI RAM access may be stalled since the 82586 is accessing the RAM and then the CTI bus transaction has to wait. Is the signal AACKAL used somehow to...

Thanks for checking this. Obviously I mixed things up. It says in the tech manual that XACKA L goes to the CTI memory Data latch so it is indeed exactly what you have written. What I wanted you to check was to check where the AACKBL (5) signal goes. It should go through a 7404 and then to...

No the ROM is not behind the 8207. The 8207 only handles DRAMs. I.e. it has row/column multiplexing logic and refresh management. There is a simple counter that addresses the ROM and each time you read from baseport+0 you get the current data from the ROM and the counter is incremented. Then if...

You should be able to rip out parts of the diagnostic that sets up mapping. I think the PAR is restored back using EMT 6 after the test is concluded. But if you just call EMT 5 with proper parameter you should have you mapping set up. Somewhere you need to write to the base register in the DECNA...

It is indeed real memory. But it is also a dual-ported shared memory. The 82586 ethernet controller has all its buffers and control structure in this space.

Remember that for examle both DECNA and the video card takes up space in this area. DECNA uses 128k. Don’t remeber the memory window of the video board. Then there might be other boards that need IO. It adds up. The Diag ROM for the memory board cleraly show that it will configure memory up to...

The big chip is a dual memory DRAM controller. It both handles DRAM refresh and RAS/CAS as well as dual port arbitration. Intel 8207.

You can have up to 3 meg in P/OS. That is the limit. You can test using my fork of Xhomer which has 3 meg support.

Actually the KDF11 microcode is dumped, at least the russian clone of the KDF11, but one can assume that it is identical. Here is a verilog model of the KDF11: 11/23 in verilog It should be possible to convert it into software and then run the microcode if one wish.