A3000 FastMem expansion ideas

[Crypticalcode0]

I am contemplating some memory expansion for the amiga 3000.
Why not use a Zorro RAM card?
They are easy to get.
However they need a high revision Buster.

What about Using a CPU upgrade?
Not all of them expand memory, and those who do are in high demand, and do not always play nice with lower revision chips.

Expanding A3000's Motherboard FastMem is impossible without disabling the SCSI.
This is a myth.

Why Do this?
To prove my above point.

What are the needed signals?
A24::A31
RAS0::RAS3
_AS
CLK90

What signals should we generate?
A10

 

[Crypticalcode0]

Adress decoding.
Options 7485, 74679, 74682, 74684 74686, 74688.

The 7485 is slightly too slow to keep up with the required frequency because it's switch time 45ns where we have 20ns because 25MHz operation.

74682, 74684, 74686 and 74688 waste many pins for this design which is not efficient energy wise because they have to be tied to a VCC or VSS line to decode besides we need 10 lines to be decoded.

This leaves the 74679 which is the hardest to get but it does respond within the desired time frame.(if you don't use the HC or HCT versions)
We need to decode the value 0000000001 A31::A26
This means that P3 needs to be tied to Vcc and atleast one of the others need to be too the others can be tied to Gnd.
We can connect _G to _AS because we need to validate the Address.

 

[Crypticalcode0]

Now there are 2 ways to this part.
One Generate MA10
Using an 74157 we can select A24 or A25 for A10, There are several Conditions that must be met.
-Never have a Unaligned access!
-Never expect the DMAC to utilize memory above the first 16MiB

Okay so what do we do this is a sloppy hack but it should work.
_G of this chip gets connected to the ouput of the address decoder mentioned previously.
A/_B is connected to CAS0.
And A24 and A25 are on MA10 respectively depending on CAS0 cycle and address decoding.


Two Multiplex RASx
Using a few 74137 you can use the address decoder to latch the valid A24 and A25 to expand the number of RAS signals.
You then use RASx to enable output.
This is an interresting technique but it makes RAS refresh rather complex.

Now here comes the big trick 2 diodes and 2 resistors you want to cut the A24 and A25 lines near Ramsey and bridge the break with a Diode so when Ramsey drives the Bus it will pull those lines near Gnd level, besides that you want a pull up resistor so they are high on Ramsey's side when he isn't driving the bus.

 

[Crypticalcode0]

reduced the number of dependency.

Needs the following signals
A24::A27
_AS
_DMAEN

It needs a cut in the traces of A25, A26, and A27

I consider this an more elegant solution for people with an A3000 it doesn't solve the needed address line generation but it does allow larger address range generation.
It requires a 74AS85 jumpers or dip-switches if you like to alter the amount of memory afterwards, it needs to be AS or faster because else you would get your address after _AS became valid.(which is bad)
you need to cut address lines A25, A26, A27
A side of the 7485 connects to A24, A25, A26, A27, B side is wired GND VCC GND GND or to jumpers or dip-switches depending on what you have on hand.(I'd advice against hard wiring because then you mirror the address space every 16MiB)
the A<B output is wired to a tri-state buffer like the 74125 of which the output is wired to the Address lines of RAMSEY the _EO the enable is wired to _AS this should work.(you could use the last buffer as a delay on the _AS if you detect a race condition)
Doing this gives you addressing space from $00000000 to $07FFFFFF the hard wired solution I gave would start at $01000000.(jumpers and switches allow increments of 8MiB)
To ensure RAMSEY can still drive the address bus when _DMAEN comes you need another 74125 which is bridging the other construction in the other direction and use _DMAEN on the _OE.

TODO:
generate MA10
possible solution 74157 or 74298