CF cards and changing PIO modes (enable IORDY)

[tom.storey]

Hi all.

I cant quite decide if this should go in the hardware or programming forums as it straddles the lines of both in certain ways, but I feel its more appropriate here.

Im trying to enable the IORDY signal on a CF card. The capabilities word obtained from an "identify" command states that it is supported (along with PIO modes 3 and 4 where this signal is mandatory).

It seems I should only need to use the "set features" command with feature 3 and supply the appropriate value, in this case 0xB (1011) to enable PIO mode 3 and IORDY.

I do this, and the drive does not report any errors in either the status or error registers suggesting that it accepted the command, but I never see the IORDY signal toggling when reading/writing after that.

Has anyone ever done anything like this before and knows the process? Ive been googling for hours looking at any and all documents about IDE, ATA, PIO, etc that I can find and they all seem to suggest about the same thing so Im not sure what Im doing wrong.

Thanks!

 

[bakemono]

Not sure about IORDY enablement, but the transfer rate is going to be controlled on the interface end, not by the storage device. If the CF card is connected to a standard PCI-IDE controller then you should be able to get PIO mode 3/4 by way of a BIOS setting or by poking PCI-IDE registers. If it's something pre-PCI then it might be a jumper setting, assuming higher PIO speeds are even supported.

Is it possible that IORDY is enabled but the signal is never used when the transfer rate is less than PIO 3?

 

[tom.storey]

Hi, thanks for the response. I found out some more in the mean time, and while the signal is mandatory for use in PIO mode 3 and above, the consensus I received seems to be that at the speeds I am trying to access the card Im probably highly unlikely to stress the card enough to provoke it in to generating the waveforms I was expecting to see.

Certainly, IORDY is not used for every bus cycle as I had thought by my interpretation of the timing diagrams in the datasheets Ive looked at. Youve really got to get in to high speed transfers for it to become a consideration.

I hadnt mentioned it, but this is for a homebrew 68k system I am building, and I am implementing my own "IDE" interface. But my plan now is to implement my controller interface in a different way, and provide a means to adjust cycle timing with a couple of bits in a register somewhere, and that will adjust the timing generated by a CPLD. It will default to mode 0 timing on reset, which should then allow you to read any attached drive, determine its capability, and then through a register somewhere set a couple of bits to adjust the CPLD timing to support faster bus cycles. I had hoped that IORDY would be a per cycle thing and that I could tie it in to DTACK generation such that the card would stretch out the bus cycles on its own as required, but that isnt quite how IORDY works as it would seem.