Compaq Portable II, Recreating the 512/1536 Kbyte System Memory Board (104176-001)

[HoJoPo]

I used the top of my little Engel 63 quart chest freezer to try to keep the camera about the same distance from the card, sliding the camera along one of the seams in the top. Seems to have worked.

 

[silvervest]

Front and back - back is mirrored to be overlaid to front so traces can be lined up

 

[btb]

wow, that is good stitching! what tools do you and your partner use for that?

Few little things:
are any of these connected to anything as far as you can tell?
Main connector ("P300") pin A3, A4, B3, B4
Z1 pin 1 (probably VCC?)
Z1 pin 2, pin 10
Z2 pin 2
Z3 pin 2
U58 pin 8, 9, 10

 

[silvervest]

Just Photoshop and a good eye (hers!)

I must be blind, but I can't see part Z1 at all
Based on their purpose (prevent DRAM ringing) Z2/Z3 pin 1 will definitely be VCC and I'm guessing pin 2 is N/C on both and 3-10 are directly connected to 11-18 on the 74S245's
U58 pins 8, 9, 10 are likely an unused gate on that 74F32 just based on positioning
Would need @HoJoPo to confirm fully, esp the P300 pins. Damn that connector hides a lot!

 

[btb]

Here's the KiCad files: https://github.com/btb/PortableIIMemBoard

Oh, I think Z1 is unlabeled, but that's what I'm calling the footprint in the upper left that looks like another resistor network.

 

[btb]

From our humble beginnings:

 

[silvervest]

Absolutely phenomenal work so far!

 

[btb]

I'm probably going to be mostly working on the SIMM version now. But the board I uploaded is most of the way there to being a reproduction of the original, if that's something you want to start tweaking

 

[HoJoPo]

U58 pin 2 and 4 connect to pin B5 (as numbered on the back of the board)
U58 pin 11 connects to U54 pin 9, then goes under U51 to connect to U51 pin 9 as well.
C70-74 aren't populated, have one pin to the ground plane, but have a trace running from them on the other side of the cap.
C70 connects to R5, other side of R5 connects to pin 3 of U1
C71 connects to R4, other side of R4 connects to pin 4 of U1
C72 connects to R8, other side of R8 connects to a via under U4
C73 connects to R6, other side of R6 connects to pin 3 of U7
C74 connects to R7, other side of R7 connects to pin 4 of U7

R1/R2 form a voltage divider, R1 connects to GND, R2 to VCC, they connect to each other and pin 1 of U17.

Looks like C70/R5 and C73/R6 are signal conditioning the WRITE signal and C71/R4 and C74/R7 are conditioning the RAS signal, if they were populated.

Minor updates for your schematic:
C70 connects to R5, other side of R5 connects to pin 3 of U1 (Bank 4)
C73 connects to R6, other side of R6 connects to pin 3 of U7 (Bank 2)

I mean, it's not wrong in that WE is connected together, but R6 does connect across the board at bank 2, not directly at bank 4.

I'll see if I can verify R8's connection, I may have to pull the chip it goes under with a via.

 

[silvervest]

Yep will do, there's a few tweaks I'd like to make and then do all the particulars around board markings and such, but otherwise it's looking pretty dang perfect. Seriously well done

Question- the trace at the bottom of the board that cuts through the BANK 2 silkscreen is unrouted. I think this might be a separated ~{WE} line for banks 3/4, maybe to keep signal integrity etc. I can't think of anything else that it would connect to there...

 

[btb]

Minor updates for your schematic:
C70 connects to R5, other side of R5 connects to pin 3 of U1 (Bank 4)
C73 connects to R6, other side of R6 connects to pin 3 of U7 (Bank 2)

I mean, it's not wrong in that WE is connected together, but R6 does connect across the board at bank 2, not directly at bank 4.

I'll see if I can verify R8's connection, I may have to pull the chip it goes under with a via.

So pin 3 of U1 and pin 3 of U7 not shorted together?

Yep will do, there's a few tweaks I'd like to make and then do all the particulars around board markings and such, but otherwise it's looking pretty dang perfect. Seriously well done

Question- the trace at the bottom of the board that cuts through the BANK 2 silkscreen is unrouted. I think this might be a separated ~{WE} line for banks 3/4, maybe to keep signal integrity etc. I can't think of anything else that it would connect to there...
View attachment 1276220

Ah yes, you're both exactly right! - there are two separate /WE signals on the board, That trace must go to pin A4. A4 and B7 are shorted together on the motherboard.

 

[HoJoPo]

For your enjoyment, an upside down front series of photos, including one I lit to see the connector more clearly.

 

[HoJoPo]

Z1 is labelled as Z1, it's hard to see because the top of the Z is the silk screen around the resistor pack, and the bottom connects to the silk screen box around U1.

A4 connects pin 3 of U46, using a trace that runs under the silkscreen box across the bottom of the connector. It goes over, through the "BANK 2" silkscreen on the bottom, and then jogs around pin 2 of U47 (without connection) to connect to pin 3 of U46.

A3, B3 and B4 appear to be NC (completely open to ground and VCC for all three pins).

 

[HoJoPo]

Z58 pins 8, 9 and 10 are NC. (under the sticker)

Z2 and Z3 pin 2 are NC. Looks like you did get that U55 pin 11 connects to Z2 pin 10 and connects Z2 pin 10 to U52 pin 2.

 

[HoJoPo]

Z1 pin 1 is VCC.
Z1 pin 2 is U1 pin 13 (top side trace)
Z1 pin 3 is U1 pin 12 (bottom side trace)
Z1 pin 4 is U1 pin 5 (top side trace, goes between pins on U1 underneath the socket)
Z1 pin 5 is U1 pin 11 (bottom side trace)
Z1 pin 6 is U1 pin 6 (top side trace, goes between pins on U1 underneath the socket)
Z1 pin 7 is U1 pin 10 (bottom side trace)
Z1 pin 8 is U1 pin 7 (top side trace, goes between pins on U1 underneath the socket)
Z1 pin 9 is U1 pin 9 (top side trace)
Z1 pin 10 is NC.

So, Z1 is connected to A0-A7, and A8 is taken care of by the R1/R2 voltage divider (none of which are installed). Interesting that A8 had to be slightly different, as they did have enough pins on Z1...

 

[HoJoPo]

R8 connects to pin 4 of U4 in bank 3, which makes sense as that's the RAS signal for bank 3.

 

[HoJoPo]

Ah, pin A4 is write enable for both bank 3 and bank 4, confirmed with the multimeter, just as silvervest had shown. Bank 2 WE is separate.

 

[btb]

nice. I think the schematic is probably fully complete now

 

[HoJoPo]

The latest schematic looks good to me, maybe move the R6/C73 labels to the other side so they don't overlap R7/C74.

 

[HoJoPo]

For the SIMM version, are you going to do 2x1MB parity 30 pin SIMMs and waste 1/4 of the RAM, or use 6x256k parity SIMMs?

Edit: Thinking this over, to work with the three RAS signals without additional logic, you'd need to do the 6x256k SIMM design. Of course, turning those signals into the additional addressing wouldn't be too difficult.