Dram refresh

[scommstech]

Hi
I'm trying to check out an old XT motherboard and have hit a problem.
Does anybody understand the memory refresh process that IBM's XTs
used.
The board uses the 4164 DRAM therfore there are 64000 memory cells
per chip.
The XT uses RAS/CAS and 16 bit addressing. I would expect RAS to use 8
Add bits 0-7 = 256, and CAS to use Add bits 8-15 = 256 thus giving a total
of 64000 memory cells.
The refresh only uses RAS every 2ms set up by the DMA. All 4 banks get RAS
at the same time. I believe that toggling RAS causes a cell refresh.
For all the 64000 cells to be refreshed each RAS toggle must have
an accompanying incrementing address 0 to 256. So 256 RAS pulses would
refresh to whole memory.
Using a logic analyzer on the faulty board the RAS pulse is accompanied by
a constant address. This I thought was the problem, ie the address not
incrementing. I put the analyzer on a good motherboard and it's the same,
ie constant address.
Where is my theory going wrong ???.
Can anybody throw some light on this.
Regards
Scommstech

 

[modem7]

Be aware that you may also encounter a type 2 XT motherboard:

Type 1 motherboard: 4 banks of 64k chips --> 256K max.
Type 2 motherboard: banks 0 and 1 have 256k chips, banks 2 and 3 have 64k chips --> 640K max.

I believe that toggling RAS causes a cell refresh. For all the 64000 cells to be refreshed each RAS toggle must have an accompanying ncrementing address 0 to 256. So 256 RAS pulses would refresh to whole memory.

Yes, as confirmed by 4164 data sheets, e.g. "Strobing each of the 256 row addresses (A0 through A7) with /RAS causes all bits in each row to be refreshed."

Using a logic analyzer on the faulty board the RAS pulse is accompanied by a constant address. This I thought was the problem, ie the address not incrementing. I put the analyzer on a good motherboard and it's the same, ie constant address. Where is my theory going wrong ???.

The address bits should be changing every so often. About now, I'd be bringing out my oscilloscope to confirm state changes.

The spec I see for the 4164 indicates that for refresh, each address would need to be read at least every 4 milliseconds.

So how is the 5160 motherboard organising that. From my reading of the 5160 Tech Reference, I see:
Channel 1 on the timer chip is set up to trigger a single refresh every 15uS (refresh done by a dummy DMA transfer) with that (row) refresh taking approx. 200nS.

|<--------- 15 uS -------->|<--------- 15 uS -------->|<--------- 15 uS -------->|<------- etc.
|R|                        |R|                        |R|                        |R|
|o|                        |o|                        |o|                        |o|
|w|                        |w|                        |w|                        |w|
|1|                        |2|                        |3|                        |4|

So with 256 rows to be done for an entire refresh cycle, the entire refresh cycle will take
256 x 15uS = 3.84mS, just within the 4mS requirement of the 4164.


Re your logic analyzer triggering.
Note that the address is not present for the entire duration of the /RAS pulse, and so just make sure that you are triggering on the falling edge of /RAS (rather than on the rising edge).
Also, some datasheets indicate that the address doesn't need to be stable until just after the falling edge.

 

[scommstech]

4164 refresh

4164 refresh

Thanks for your input.
You got me thinking on that XT and 2XT board.
I have a few faulty boards and remember one having a full population
of memory and some memory chips were different. It may be this board.
I actually removed the memory and just used bank 0 with 4164s for testing.
I am using a RACER II diag XT card to run memory tests. The write up says it
ignores the board dip switches so I assumed using just one bank would not
be a problem Maybe it is.
The RACER II initially checks the DMA and timer chip. It passes these two but then fails on refresh and memory.
I'm sure it is a timing prob as some times the RACER passes a few
random RAM chips. This is usually after Iv'e got analyzer test leads hanging
onto the memory chip legs. (bit 7)
So thanks for the DMA timing info. Thats one thing I have not checked.
I just saw the RAS and accepted that they were timed right.
Rgs
Scommstech