vrs42
Veteran Member
I should note that at present the TTL implementation has been talked about, but AFAIK no one has committed to actually do it.Please count me in for at least 2 maybe 3 of your EAE boards/sets.
I do have prototypes of the CPLD version, but people don't seem super excited about it, and I've got dozens of similar half finished projects to chose from, so it hasn't been a priority.
Well, there it gets interesting. A Verilog extraction for the TC08 exists, and has even been fully debugged in an FPGA (with a TU56 drive emulation), thanks to Kyle. So what remains there is basically to take that and figure out an attractive implementation.With all this talk of TD8E controllers how hard would it be to make a TC08 TTL clone? I know the TC08 required both a KA8E (Positive I/O) and a KD8E (Data Break) boards. The ideal TC08 redux would be a single board with KA8E & KD8E on board. Or maybe a two board set. Kind of like the RK8E which included the Data Break in the three board set.
As a DMA device, it is likely just a little too large for a single CPLD, so the code would have to be partitioned into a couple of parts. (I admit that I haven't actually tried to fit it into a single CPLD, though.)
An FPGA could be used, as Kyle has done, but then interfacing to vintage gear becomes more problematic. (Kyle's FPGA version just implements the whole 8/i CPU Verilog extraction as well.)
As far as the Omnibus interface, you've outlines the basics. I'd probably do a card with TA8E and KD8E functions on it, and let folks populate either or both parts.
Vince