How does dynamic RAM work?

[NicolasF]

I'm interested in learning about how old dynamic RAM works, for example chips like 41256 or 4164.
I've been trying to search for application notes or some kind of book that will explain how to make them work but I haven't been able to find anything serious.
Does anyone have any information about this?

Thanks!

 

[KC9UDX]

Black magic; pure evil. :-x

If you search the web for "4164 DRAM datasheet", I think you will find what you are looking for.

I don't mean to be a "do it for yourself" snob but it's difficult for me to post a link from here.

 

[Scali]

Isn't this what you're looking for? https://en.wikipedia.org/wiki/Dynam...s_to_read_a_data_bit_from_a_DRAM_storage_cell
As far as I know it's as 'simple' as:
1) Set RAS high and put row address on the address lines.
2) Enable the write line if you want to write.
3) Set CAS high and put column address on the address lines.
4) Requested bit(s) output on the data lines for a read, or bit(s) on data lines written to memory.
5) Make RAS and CAS low to complete the cycle.

(The reason for separate rows and columns in the addressing cycle is because the addresses are multiplexed, to minimize the number of address lines required).

Of course this all needs to be done with proper timing, no faster than what the memory can handle.

Don't forget to set up a refresh cycle that periodically triggers a read of each row in your memory (the row access triggers a refresh of the entire row, so no need to access every individual column), to prevent data loss.

 

[Plasma]

There are probably a hundred articles online about DRAM operation...first google result

https://www.ece.cmu.edu/~ece548/localcpy/dramop.pdf