I like your idea Ruud! I've been thinking on an accelerator design based on a V30 cpu. My understanding of the hardware interface is we would need to produce an extra bus cycle on 16 bit transfers because we can only get 8 bits at a time. Maybe this could be accomplished with a counter and a ROM to produce the signals for those transfers when needed. The accelerator would have on-board 16-bit RAM and could probably ignore the 8-bit ram on the motherboard after boot, which I believe is similar to the inboard 386, and could cache the BIOS ROMs into the 16-bit RAM. Still gotta figure out how to handle DMA transfers. Inspiration for the design would be the Quadram Quadsprint which is based on an 8086.