Switching between two 8088 CPUs

[1ST1]

This one might help:





Maybe you can use the HOLD signal to stop the 8088.




You might put a switch between the hold signal from the mainboard and the pin 31 hold of the two CPUs and a pullup to 5V. Maybe this would stop one of the CPUs. The 2nd swithch must be like above to trigger reset while switching.

 

[jplr]

I would say that it is more complicated than a mechanical switch:
* You have to debounce the mechanical switches.
* You have to make sure you are in Minimum mode (MN/MX pin is wired high) otherwise it's a different logic that applies: RQ/GT0 and RQ/GT1 are bidirectional.
* After requesting Hold, you have to wait for HLDA
* There are special cases that must be managed such as interrupts from other circuits and external cards (not only in terms of hardware but also software)
* HLDA , ALE and INTA are not tri-stated so there is a need for more circuitry.
* What about DMA access? How do you manage them? How to share hold/hlda with other circuits?

A close look at the 8086 processor's bus hold circuitry

The Intel 8086 microprocessor (1978) revolutionized computing by founding the x86 architecture that continues to this day. One of the less...

www.righto.com

Why are ALE and INTA not floated during Hold on an 8088 while other outputs are?

When the 8088 goes into hold, every output is tri-stated apart from HLDA (obviously), ALE and INTA. Given that the purpose of hold is to allow an external device to control the bus, like a DMA cont...

electronics.stackexchange.com

 

[GloriousCow]

I would say that it is more complicated than a mechanical switch:
* You have to debounce the mechanical switches.
* You have to make sure you are in Minimum mode (MN/MX pin is wired high) otherwise it's a different logic that applies: RQ/GT0 and RQ/GT1 are bidirectional.

You can't just run the CPU in the PC in minimum mode, all the bus signals are hooked up to the 8288, which can't understand the CPU in minimum mode.

DMA, strangely enough, isn't a problem. The DMA controller doesn't do bus mastering, the motherboard DMA logic just pulls the ready line low and the DMA controller does its thing - if the CPU tries to access the bus at the same time it will hit wait states until DMA is complete.