saipan59
Experienced Member
Some of you may recall that 5 years ago I made a PCB for a minimal T-11 system in "8-bit static" mode. This thread discussed it:
http://www.vcfed.org/forum/showthread.php?47569-T11-clock-running-Forth&p=369704#post369704
And you may recall that there was an 'issue' related to the MC6850 UART that I chose to use. It was some sort of timing/bus loading issue, but I never really figured it out. It "worked" when I did NOT use a 74LS part on the data bus for GPIO, but rather used a 74HCT part.
The prototype was a wire-wrap board which I still have.
This week, I started working on making two changes to the wire-wrap "development system":
1) Replace the MC6850 with an AY3-1015D, to make everything "proper" on the data bus. (Note that the AY3-1015D, AY5-1013, and 6402 (aka 64S004B) are used in various DEC boards, and they're all roughly the same part). Also adding enough logic to implement the CSR bits for "Rcvr Ready" and "Xmtr Done". Adding other CSR bits is easy, but I don't need them at the moment.
2) Change the addressing so that the UART is at 176500 (the common console port address), instead of 160000.
These changes will get me very close to having the same Forth code image that runs on my LSI-11 + MXV11 Qbus setup.
Here are pics of the board. The ugly wire-wrapping could be called a "rat's nest", or we could just call it "distributed reactance" and say it is a "feature" ;-) .
The new UART is just below and to the left of the blue ZIF socket (for the EEPROM). The T-11 is above and to the left of the ZIF. The 3 rows of chips on the bottom are a separate system - it is a simple ASCII terminal, running an MC68701, with a 2-line 40-column LCD display at the very bottom.
Pete


http://www.vcfed.org/forum/showthread.php?47569-T11-clock-running-Forth&p=369704#post369704
And you may recall that there was an 'issue' related to the MC6850 UART that I chose to use. It was some sort of timing/bus loading issue, but I never really figured it out. It "worked" when I did NOT use a 74LS part on the data bus for GPIO, but rather used a 74HCT part.
The prototype was a wire-wrap board which I still have.
This week, I started working on making two changes to the wire-wrap "development system":
1) Replace the MC6850 with an AY3-1015D, to make everything "proper" on the data bus. (Note that the AY3-1015D, AY5-1013, and 6402 (aka 64S004B) are used in various DEC boards, and they're all roughly the same part). Also adding enough logic to implement the CSR bits for "Rcvr Ready" and "Xmtr Done". Adding other CSR bits is easy, but I don't need them at the moment.
2) Change the addressing so that the UART is at 176500 (the common console port address), instead of 160000.
These changes will get me very close to having the same Forth code image that runs on my LSI-11 + MXV11 Qbus setup.
Here are pics of the board. The ugly wire-wrapping could be called a "rat's nest", or we could just call it "distributed reactance" and say it is a "feature" ;-) .
The new UART is just below and to the left of the blue ZIF socket (for the EEPROM). The T-11 is above and to the left of the ZIF. The 3 rows of chips on the bottom are a separate system - it is a simple ASCII terminal, running an MC68701, with a 2-line 40-column LCD display at the very bottom.
Pete

