The F11 and J11 odd data address trap

[vol.litwr]

The Xhomer emulator doesn't generate a trap on an odd data address. Does the F11 generate such a trap? I know that the J11 generates it. But I am not aware is it possible to disable this J11 feature? A lot of thanks in advance.

EDIT. How do I determine which is being used, the F11 or J11?

 

[czunit]

Yeah, that is an old surprise. I don't think odd address was supposed to be done but F11's never minded so people did it.

 

[Radix]

11/23 do not trap on odd addresses - an the original BDV11 bootstrap code contained at least one so it didn't work on an 11/73, use the MFPT instruction to get a value for the cpu type on 11/23 and later, 11/23 returns 3 in R0

 

[czunit]

The 11/03 didn't, did the 11/45,44,or 70?

 

[AK6DN]

The 11/03 didn't, did the 11/45,44,or 70?

All the discrete TTL implementations of PDP-11 CPUs had an odd address trap.
LSI11, T11, and F11 did not; J11 did. So YMMV depending on the PDP-11 chip level implementation you have.
Based on hazy recollection and confirmation by the PDP-11 Processor Handbook 1985 appendix page A-15 CPU differences table.

 

[czunit]

Ok. So this is just another one of those oddball things like the stunt you could pull by running programs in the pdp11/05's registers (faster!). Same trick was done on a KA10 but I don't know of any other 11 that would allow it.

 

[AK6DN]

Ok. So this is just another one of those oddball things like the stunt you could pull by running programs in the pdp11/05's registers (faster!). Same trick was done on a KA10 but I don't know of any other 11 that would allow it.

Same book, page A-14 CPU differences only the 11/05-10 allows GPR reference from an I/O page address.