antiquekid3
Veteran Member
Over the last month or so, I've been converting Flip-Chip modules from schematics to Verilog, mostly by hand. With much help from Vince Slyngstad, we converted his wonderful, digitized PDP-8/I drawings to a Verilog netlist that instantiates all of my modules. After many hours of debugging, and even uncovering the very rare error in Vince's schematics, the PDP-8/I model came to life and executed a variety of MAINDECs--correctly, even!
But, I couldn't stop there. It's not a real PDP-8 unless it can boot OS/8, so for that, I turned to modeling the TC08 and a TU55. The TC08 was developed in the same way as the PDP-8/I: Vince's schematics plus custom Flip-Chip Verilog models. The TU55 is just an approximation of one at this point, but it's close enough to work. I'll work on adding write support and increasing the fidelity of the transport model soon.
The goal of this project was not to create a Verilog PDP-8 with peripherals. That already exists. Actually, many implementations already exist. The goal of this project was to preserve the original implementation at the Flip-Chip level. I believe the success of this so far proves that this is a viable technique for bringing life to other PDP machines--and other computers as well. Someday, I hope to have a library of Flip-Chip (and System) modules, along with models of certain logic chip families used on the later integrated modules, such that the only thing required to bring up a new computer is the backplane netlist, derived from digitized schematics or otherwise. This can also be a great debugging technique, since nearly every backplane connection is available for viewing with GTKWave, which can then be compared to any oscilloscope or logic analyzer traces. This also provides a test platform for testing new peripherals and such, by providing a logically-accurate Negibus and Posibus.
There are some limitations in this approach, namely the core memory components have all vanished and have been replaced with a simple memory module instead.
Without further ado: https://github.com/drovak/verilogpdp
I still haven't targeted an FPGA yet, but that is in the works. Right now, it simulates (very slowly) with Verilator. You'll get to the dot prompt after a few minutes, and if you're patient enough, you'll eventually get a directory listing after typing "DIR". Better plan to get breakfast, lunch, or dinner while you wait, as it takes about an hour to get there on my computer.
If anyone wishes to contribute Flip-Chip Verilog models for other PDPs or peripherals, that would be excellent. If anyone wants to target an FPGA development board, please feel free to send over the project directory and I'll try to incorporate that as well.
Enjoy,
Kyle
But, I couldn't stop there. It's not a real PDP-8 unless it can boot OS/8, so for that, I turned to modeling the TC08 and a TU55. The TC08 was developed in the same way as the PDP-8/I: Vince's schematics plus custom Flip-Chip Verilog models. The TU55 is just an approximation of one at this point, but it's close enough to work. I'll work on adding write support and increasing the fidelity of the transport model soon.
The goal of this project was not to create a Verilog PDP-8 with peripherals. That already exists. Actually, many implementations already exist. The goal of this project was to preserve the original implementation at the Flip-Chip level. I believe the success of this so far proves that this is a viable technique for bringing life to other PDP machines--and other computers as well. Someday, I hope to have a library of Flip-Chip (and System) modules, along with models of certain logic chip families used on the later integrated modules, such that the only thing required to bring up a new computer is the backplane netlist, derived from digitized schematics or otherwise. This can also be a great debugging technique, since nearly every backplane connection is available for viewing with GTKWave, which can then be compared to any oscilloscope or logic analyzer traces. This also provides a test platform for testing new peripherals and such, by providing a logically-accurate Negibus and Posibus.
There are some limitations in this approach, namely the core memory components have all vanished and have been replaced with a simple memory module instead.
Without further ado: https://github.com/drovak/verilogpdp
I still haven't targeted an FPGA yet, but that is in the works. Right now, it simulates (very slowly) with Verilator. You'll get to the dot prompt after a few minutes, and if you're patient enough, you'll eventually get a directory listing after typing "DIR". Better plan to get breakfast, lunch, or dinner while you wait, as it takes about an hour to get there on my computer.
If anyone wishes to contribute Flip-Chip Verilog models for other PDPs or peripherals, that would be excellent. If anyone wants to target an FPGA development board, please feel free to send over the project directory and I'll try to incorporate that as well.
Enjoy,
Kyle
