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wanted: 80486 motherboard or laptop/notebook schematics

NobodyIsHere

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Hi
I am looking for 80486 motherboard or laptop/notebook schematics preferably with OPTi chipset but *any* would be helpful.

Specifically the OPTi 82C465MVB or 82C495XLC chipsets would be ideal. After several days of looking I have yet to find even a single 80486 motherboard or laptop/notebook schematic. Even 80386 schematics are rare and I haven't seen any yet.

A total jackpot would be if someone has the following document which OPTi published on their BBS back around about 1994 or so. They refer to it in their 82C465MV datasheet (rev 2.0) but its not available on what's left of their website.

OPTi 82C465MV+82C602 Demonstration Board Schematics. Printed version and OrCAD files both available; files also available on BBS (see Appendix A., Accessing the BBS)

Any help greatly appreciated.

PS, these were fairly common 80486 chipsets back in the day. There were also some 80486 laptops built using OPTi chipsets such as the Zenith Z Star EX
 
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eeguru

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Andrew,

I've been lurking on the retro brew forums loosely following your 486 design discussions but am just too busy to register for another daily rabbit hole. :) I got the impression the group was unaware of the efforts put in by John Monahan at s100computers.com on his 486 board:

http://www.s100computers.com/My System Pages/80486 Board/80486 CPU Board.htm

It might be a good first stepping stone to build on as he's put in quite a lot of hard work solving the really difficult timing problems and produced a fantastic piece of engineering in the process.

I also produced a prototype local bus memory expansion board for his 386/486 designs supporting up to 4GB of memory, however due to real life obligations and some other more imminent vintage projects, it has gotten pushed way down on my priority list atm (sorry John). It's been stalled without code development since effectively version 1 when I ran into a conductive noise emission problem with TXB0104/8 buffer devices from TI. The board itself needs a respin to be functional coupled to one of the CPU boards. However the memory controller firmware can be moved forward in parallel. I planned on extending a 16-bit SDRAM controller I had written for my mini-386 project a while back. I can gather up and post more info after I get back from VCF-East. Or if anyone from the retro brew forums will be in NJ, we can discuss in person.

-Alan
 
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NobodyIsHere

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Hi, Thanks

Yes, I am aware of John's 80486 S-100 board. It is a very ambitious project. I am going more for a PC/AT 80486 compatible design which if I can use an integrated chipset like OPTi 82C465MVB+82C602 should be a lot easier and less ambitious to implement. It is the 80486 CPU to bus interface glue logic where John did a lot of work. Hopefully the integrated PC/AT chipsets for ISA will handle that magic.

However your 4GB board (SDRAM, I presume) might be helpful on the Gryphon 68030 or Alderaan 68040 projects which are facing similar issues. If you have information to post you might want to consider posting it so the 680x0 projects could use it and possibly further its development.
 

NobodyIsHere

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Hi
Yes, I have the rev 3.0 of the datasheet and it is a little better. Still it would be very helpful to have a reference schematic to compare. I can implement from a datasheet only but there are always gaps no matter how well written and you just fill them in as best you can from experience. A reference schematic, even one using a different chipset, would be a helpful guide. But this isn't a case of LMGTFY as I have searched high and low already.
 

NobodyIsHere

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Hi

Anyone have any other ideas on a 80486 mainboard schematic? It doesn't necessarily have to be a PC motherboard, it could be a laptop/notebook or even some embedded computer. Literally the only thing I can find is John Monahan's S-100 80486 board schematics and the PC/AT technical reference schematic. The PC/AT is 80286 CPU but still very helpful in explaining some of the vagaries of late 1980's early 1990's PC computer design. Much of it carried over to the 80486 series.
 

NobodyIsHere

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I swear once I saw a web page with someone's 80486 project (engineering school?) made out of perf-board and wire-wrapped. It was a SBC but not a PC/AT mainboard. All I remember was it had SRAM, EPROM, a PIT chip, and some kind of simple keypad & LED read-out. It was pretty simple but even that would be helpful if I could ever find it again. Unfortunately I didn't keep the link :-(

Why is there almost no hobbyist project information on the 80486? It seems like there is practically none on the 80386 too. It seems odd to me.
 

NobodyIsHere

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OK, well it seems like there aren't many, if any, 486 board schematics available so let's try a different tack.

Is there anyone who is experienced with 486 board design who would also like to collaborate on a 486 home brew project?

I have written a schematic based on 486, 82C465MVB, 82C602A, and PC97338 chips. It is complete and I am reviewing and checking/re-checking the assumptions. However it is complex and would appreciate some independent review so the initial build and test has the best chance of succeeding possible. The plan is for the circuit to fit on a full size AT ISA board and plug into a passive AT ISA backplane similar to the Xi-8088 board.

Thanks, Andrew Lynch
 

zombienerd

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Well, I just found this page, which includes schematics for a few 486 based SBC's... Not sure what chipset it uses, but it offers full board schematics at the very bottom of the page!! (Right click and Save-as, in-browser display doesn't seem to function for me) Also includes bill of materials to order everything to build your own.

http://www.s100computers.com/My System Pages/80486 Board/80486 CPU Board.htm
 

NobodyIsHere

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Thanks, yes, those are the John Monahan 486 S-100 boards and I am familiar with those. Thanks, Andrew Lynch
 

zombienerd

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This is the full schematic set for the Intel 486sx Low Power Development Board. Postscript and Cad files included (Check the Readme). Manual for the board is included. This took me figuratively forever to find, but for some reason, your cause has stuck with me for the past day or two :)

I hope this helps, but it may just be another dead end. If so, just pat me on the head, and I'll resume my search!

https://www.dropbox.com/s/9rxglxbj4j44whe/intel 486sx devboard.rar?dl=0
 

NobodyIsHere

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HI
WOW! Well I can't see the files at the moment but I am very excited. Thanks! Please do keep up the great searching. I do appreciate your help! Great job! Thanks, Andrew Lynch

PS, would someone please post a PDF of the schematic from the new source (if that's possible)? Thanks, Andrew Lynch
 
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zombienerd

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I distilled the Postscripts into PDF, 11x17 size, very readable. I don't have Orcad 3.22 either, so I can't open the originals to see if there's anything that wasn't in the PS files, but it's a start.

https://www.dropbox.com/s/1zeonwed749kl6c/intel 486sx devboard PDFs.rar?dl=0

You can thank the Romanians. One of their college laboratories had the schematics archived with the original Intel file name. Combination of combing intel's website on the wayback machine, and some index of searches finally hit that paydirt.
 
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NobodyIsHere

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I also produced a prototype local bus memory expansion board for his 386/486 designs supporting up to 4GB of memory, however due to real life obligations and some other more imminent vintage projects, it has gotten pushed way down on my priority list atm (sorry John). It's been stalled without code development since effectively version 1 when I ran into a conductive noise emission problem with TXB0104/8 buffer devices from TI. The board itself needs a respin to be functional coupled to one of the CPU boards. However the memory controller firmware can be moved forward in parallel. I planned on extending a 16-bit SDRAM controller I had written for my mini-386 project a while back. I can gather up and post more info after I get back from VCF-East. Or if anyone from the retro brew forums will be in NJ, we can discuss in person.

-Alan

Hi Alan
Would you post or send me a schematic or picture of your memory expansion prototype? I presume it is on the 486 CPU local bus.

Would you be interested in functionally coupling your design into the 486 ISA SBC board I am working on? We are considering a similar mod for Phase 2 of the Linux-SBC once we get the basic system working.

I am almost certain the 486 ISA board will use 4 layer PCBs with power planes in the middle layers. That should help lower conductive noise significantly. Also plenty of filter caps.
 

eeguru

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Sure. I really need to get back to working on the RTL code for it. I feel terrible about leaving John out in the cold over a year ago. But life, etc... It will be at least a month and a half before I can potentially get back to working on it; eg after VCF-SE 5.0. The main issue that caused the stall was noise conductively radiating back onto the memory board from the 386 test daughter card (only for test) you can see plugged into the board in the photo. The buffers are the main culprit. I can, however, get the memory controller ported over from my 386mini project to the larger 32-bit/4GB design using a soft-core in the FPGA without needing a respin.

Photo of the board:
https://www.retrotronics.org/svn/s1004g/trunk/hardware/RevB_386.jpg

I've pushed the Eagle files, printed (PDF) schematic and layout, and the 16-bit SDR SDRAM controller I wrote for my mini386 into the SVN repo link below.
https://www.retrotronics.org/svn/s1004g/trunk
 

NobodyIsHere

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Thanks! Well it will be quite a while before we are ready to start the Phase 2 of the Linux-SBC project but it doesn't hurt to think about it. I can't see your photo at the moment but am thinking that coupling the design onto the same board and keeping it in close proximity to the 486 would reduce the need for buffers but not the level converters. Using a 4 layer PCB with robust power planes and generous filter caps should help a lot too.

What sort of FPGA are you using? I am guessing this is similar to a regular DRAM controller (DP8422V) but for SDRAM instead? Just from a pin management view point, I'd guess the address bus and control signals are going through the FPGA and the CPU data bus lines are going straight to the SDRAM. Is that correct? Otherwise you'd need an enormous FPGA will a LOT of pins.
 

eeguru

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John used an 'overhead' bus design in his S100 systems. It carries 5V signals including 30 address lines, 4 byte enables, 32 data lines, and various strobes. The address decoding was meant to be done in the FPGA and a feedback signal provided to the CPU board to tell it the RAM board could service the request or not. This was so lower 1MB conventional memory and option ROMs could optionally be served from the memory board and not the S100 bus where <1MB is typically directed.

The buffers I'm speaking of are mostly dual voltage '245s that translate 5V signaling from the CPU board to 3.3V I/O used by the FPGA and RAM. All 73 level translated local bus signals terminate on the FPGA. 68 signals go to four 168 pin DIMM sockets with the upper and lower halves of the 64-bit data bus folded over using DQMs to select each half. That leaves only 5 free I/O pins on a 208 pin package for the DIMM I2C bus, a local oscillator, and 2 for a debugging UART.

It should be possible to support mixed sized DIMMs with each one stacking sequentially at a starting base address. All DIMMs must be SDR SDRAM and 3.3V. They can be registered or unregistered as long as all DIMMs are consistently buffered or not.

The whole project is a bit of a lark. No 386/486 system needs 4GB of RAM. It's not even supported on most Pentium system as 1GB if physical space is hi-jacked for PCI access. I'm not aware of any 386 or 486 system that attempted to fully populate the physical address space. That's the main motivating factor. Even 64MB is considered gargantuan for 386/486 systems of the era. Beware of how many days the POST memory test will take!
 
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