Weird memory corruptions

[per]

I've been working on a memory daugthercard for an expansion to the Tiki-100 computer, but I'm having problems with odd data-corruptions whenever I try to use it.

This far I've made a prototype PCB I've etched myself, and I've made one using a factory-made PCB. Both show a somewhat similar behaviour: At very spesiffic address patterns, in the entire RAM and not just at the dedicated expansion area. It's almost always addresses ending with 111000xx00 that gets corrupted, the higer in memory the worse it gets. It's seemingly random, but the number of corruptions at different address areas are more or less the same.

I've tested for several things. Very first I used the factory-made PCB, thinking something was wrong with the prototype. Then I swapped RAM chips with some in the system itself, but the RAM chips were fine. Thinking there must have been something wrong with the soldering, I reflowed everything but still no success.

But just now I thought about that maybe there was something wrong with the timing. Originally the card had 41256 style DRAM chips rated for 150ns, but when I got memory for the daugthercard I got a whole bunch of 80ns Intel 21456 chips. Since these had slightly thinner plastic packages, I replaced all the original chips with the 80ns version (it's a very tight fit, about 2mm clearing to the metal top plate with the sockets I'm using). Going back to the original chips on the main card, then it works with the daugthercard without giving errors (only problem is that now I need a few more to put in the daugthercard).

What's puzzling me is that the 80ns chips work very fine when I only use them in the two banks originally on the card (0-512K). Used together with the memory daugthercard (512K-768K), it fails every single time with the same weird corruption patterns.

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For testing I use a program in ROM that rep stosb a 4K block of data at a time, then tries to xor the whole thing with the original byte pattern to check for errors.

All memory banks have their own separate /RAS line, otherwise they share the exact same input signals.

 

[Stone]

Just for sh*ts & giggles, try replacing one or two (in each bank) of the 80ns chips with one or two of the 150ns chips.

Or, fill the remaining slots on the daughtercard with some of the 150ns chips. You must know that it's OK to mix chips of different speeds within a bank. The result is that the bank runs at the speed of the slowest chip(s).

 

[per]

My main suspicion is that it's a noise-related problem though, but I've never heard of such a case. There are after all two busy, non-terminated busses in pretty close proximity to the daugthercard (one on the expansion board and one on the motherboard).

Seems like I get the best results with 150ns chips on the home-made prototype daugthercard. It's using 1970s funnel-style sockets (the really old ones without a plastic frame), and those got quite a bit more metal in them than the modern sockets. Didn't even give one corruption with 80ns chips in bank 2. Testing the first two banks with this setup at the moment!

Update: Bank 1 is good with this setup as well, but Bank 2 with 80ns chips still report a few corruptions. Way less than before, though.

 

[modem7]

You must know that it's OK to mix chips of different speeds within a bank. The result is that the bank runs at the speed of the slowest chip(s).

'Modern' motherboards have chipsets that enable dynamic memory timing, and the BIOS can adjust that timing based on its interrogation of the RAM modules.
The Tiki-100 is circa 1984. The RAM timing on the motherboard (and Per's daughtercard) is going to be fixed.

... Used together with the memory daugthercard (512K-768K)

You've verified that the Tiki-100's design is such that its dynamic RAM refresh circuitry covers that address range?

My main suspicion is that it's a noise-related problem though, but I've never heard of such a case.

See the section that starts on page 51 of the 'Design and PCB Layout Considerations for Dynamic Memories interfaced to the Z80 CPU' document at [here].

 

[per]

You've verified that the Tiki-100's design is such that its dynamic RAM refresh circuitry covers that address range?

Yep, /CAS and /RAS is steadily pulsing for all banks, even when no access. The 8088 card also has to refresh the Z80 memory mapped at 768-832KB when it has bus control.

See the section that starts on page 51 of the 'Design and PCB Layout Considerations for Dynamic Memories interfaced to the Z80 CPU' document at [here].

[/quote]
Thanks a lot! That might explain it; I'm using 100nF caps for bypass since this is what's used on the 8088 card, but I don't have the 4.7uF Tantalum caps mentioned. I might at first try with the suggested 330nF caps and see if that improves the results.

 

[modem7]

Thanks a lot! That might explain it; I'm using 100nF caps for bypass since this is what's used on the 8088 card, but I don't have the 4.7uF Tantalum caps mentioned. I might at first try with the suggested 330nF caps and see if that improves the results.

It may or may not, because the large value tantalums near the rows are important too ('feeding' the smaller caps).
In the RAM card pictured at [here], you can see that IBM decided to use two 10 uF tantalums per row.