winbond w83787if EXTADP/Extension Adapter Mode (Bus on LPT)

[stecdose]

Hi,

I got a 16bit ISA controller with 2x COM, 1x LPT, 1x game, 1x IDE, 1x FD.

The datasheet* tells about "Extension Adapter Mode". (Page 44, 46, 59)

This is a stripped down ISA Bus with just 3 address lines.
These are the signals:
/XWR
/XRD
XD0-XD7
XA0-XA2
XIRQ
XDRQ
/XDACK
TC

13 Signals for a basic bus + 3 for DMA.
The datasheet does not tell about speed as far as i can see, there are just timing diagrams which could help estimate, i think.

I simply would have to enable this mode in the controller's configuration registers. After this it's register CR2 is used for holding an user-defined address. Everytime this address matches, A0-A2. D0-D7, RD, WR is going to the DB25 connector.

It looks like it is pretty simple to do IO with 74138 and 8 latches.

I haven't found anything on this EXTADP-mode on the internet, except for a few similar winbond controller datasheets. But these also not telling me more...

My system for testing this controller is a 486-sbc. I disabled the HDC and FDC by jumpers, plugged in, and my system still boots from internal controller, as well as floppy is still working. So now i have to figure out with COM port gets which address (already 2 on the sbc) and IRQ+address jumpers for the LPT.

As the HDC is disabled, there is an GPIO pin free (IDE_D7 / GIO1, pin def datasheet p15) that can be bused as a "general purpose CS"
Datasheet says i can configure an address (GIO1AD0 - GIO1AD10) as well as a decoding mode (GIO1 ADR MODE0/GIO1 ADR MODE1) (page 79, 80, 81).
- 1 byte decode (Compare GIO1ADR10~0 with SA10~0)
- 2 bytes decode (Compare GIO1ADR10~1 with SA10~1)
- 4 bytes decode (Compare GIO1ADR10~2 with SA10~2)
- 8 bytes decode (Compare GIO1ADR10~3 with SA10~3)

I can also configure the type of CS it will be:
" When (AEN=L) & (IOW =L or IOR =L) & (SA10~0=GIO0AD10~0) ,
the pin will be activated. The active level is defined in CR14.bit4
and the IORN or IOWN are defined in CR14.bit3~2. "

This page http://www.cryogenius.com/hardware/isacard/ shows a simple ISA IO card. My idea is, i could "glue" some prototyping board to that (very small) controller i have and use the address decoder for 2x 74245 + 2x74273 for 16bit IO like shown in last link.

The much simpler thing looks like that EXTADP mode. But i would love to have a bit output port with readback and output-disable (so that i get bi-dir).

Do you guys have any suggestions or maybe a link to information on this EXTADP mode?

I just found a dead link to a program called (W83787 EFDR register reader) http://as.rumia.edu.pl/artur/ftp/bascom/pdf/Interfacing PC/index.html.



* http://pdf.datasheetcatalog.com/datasheets2/17/1793286_1.pdf
* https://4donline.ihs.com/images/Vip...0-1.pdf?hkey=EF798316E3902B6ED9A73243A3159BB0

 

[stecdose]

It seems that no one has heard about this topic, so i worked out a lot by myself and now i want to publish this information.

I hope this won't be a monologue, as it's a stripped-down ISA-bus, others should know enough to reply...

I found another Winbond controller, that supports this EXTADP mode. It's an ASUS SP97V equipped with an Pentium MMX 200 + w83877.
I installed a small linux system on it, an old 2.4-kernel+gcc.

Prior to experiments i built a "bus-debugging-tool", that is just a few LEDs+drivers, a button and connectors. The LEDs show the state of XD0-XD7, /XRD, /XRW, XA0-XA2, IRQ.

After this i used a breadboard to build an 8bit output port, like shown in my first post on this page http://www.cryogenius.com/hardware/isacard/ .

I just have drawn a schematic. There is an address decoder with two 74HCT138 + 74HCT14 inverter. Each '138 is used for decoding when reading or writing.
The inverter is needed for the CLK input of the 74273.
The '245 is the bus driver, it's direction is controlled by /XRD line. It's output is enabled by ORing /XRD and /XWR, if one of these goes low, '245 is enabled. As I could'nt find a unused OR gate in my boxes (only desoldered ones...) i used diodes and a pullup resistor. The voltage levels after the diodes are unknown atm, but with HCT logic it should still be enough.

I don't have much time now, it's just a quick overview of what I've done. I attached schematics and a piece of code (very ugly) that works.
I've tested under PC-DOS 5.02, MS DOS 6.22, Linux 2.4, Linux 2.6.

Next things to do are:
* connect 74273 directly to XD0-XD7, RST to VCC, CLK to /XWR (inverted) => this should give me output on all 8 addresses with less parts
* connect MAX7218 8 digit 7 segment driver
* connect different ADCs

In common, if a chips has R/W, CS, max 3 addr and 8 datalines, you could connect it very easily.

I hope to get some reply...

 

[stecdose]

Hmmm is my last post (2 or 3 days ago) still not approved or is it lost?
It took me quite a while to write down everything, preparing code and drawing schematics...

Here's how to connect a single '273 in EXTADP mode. It listens on all 8 addresses.
The the improvements over a direct parport connection are:
- It is faster than my parport, even tough it is the same way they are talked to (outb(data, addr))
- You can set a different address, like 0x300 (a lot of ISA dev-boards used this address) or 0x380 (free in almost every PC).

I wonder, why i don't need an inverter between /XWR and the CLK input of the 273. The 273 takes data on rising edge. But when /XWR goes high again, data shouldn't be valid anymore in my opinion. The falling edge of /XWR should mark the point of valid data...

Maybe someone has an explanation for this...