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S-100 68K CPU board project

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NobodyIsHere

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Hi! I've made this offer on CCTALK and thought should probably do the same here.

I’ve received permission from the author of “68000 Microcomputer Systems Designing and Troubleshooting” to include the S-100 68K CPU board as part of the N8VEM home brew computing project for educational purposes. This is a classic text found in many computer science and engineering courses in the 1980’s and 1990’s. It is possible some here recall the book from their own college and/or professional experiences.

http://www.amazon.com/68000-Microco...r_1_1?s=gateway&ie=UTF8&qid=1285587152&sr=8-1

As part of that effort, I am capturing the schematic and PCB layout from the book as closely as possible. The intent is to replicate the authors’ original board. There is a draft schematic and PCB layout on the N8VEM wiki here:

http://n8vem-sbc.pbworks.com/browse/#view=ViewFolder&param=S-100%2068K%20CPU

If anyone is interested in helping with this project please contact me. In particular, I am looking for volunteers to review the schematic and compare it against the schematic and PCB layout in the book. Due to the complexity of this board quality assurance is extremely important. Actually if anyone has one of these boards or experience with them I would be very interested in hearing from you.

The plan is to make a limited run of manufactured prototype PCBs to do an initial build and test of the board. If you are an experienced builder and interested in participating in the initial build and test please contact me. The corrections/updates from the prototype board will be incorporated into a board to be made available for all the N8VEM builders as part of the S-100 project.

Thanks and have a nice day!

Andrew Lynch
 
Andrew,
I'm not a layout expert, but it looks like the tight routing may result with a poor yield. I'm not sure it meets good design practice with regard to pad clearance and line spacing. It appears that the +5V is daisy-chained instead of having a separate voltage plane. It may be a little noisy although I see that it is intended to run at only 3 MHz so that my help. Is this a proven design with many build and operating?
-Dave
 
Hi! The schematic and PCB layout is from the book as consistent with the author's original design as I can make it. Don't sweat the trace routing yet though I only just started the trace route optimization and the PCB will clean up dramatically before it is done. The board is packed with ICs though no doubt about it. There is about 60 IC packages on the board which is really pushing it for S-100 2 layer form factor.

I am thinking the original boards were only wire wrap units since the density certainly is pushing 2 layer PCB component density. I think 2 layer is workable though with plenty of decoupling capacitors and ground fill zones. We've had good luck with the other S-100 boards we've made and they are all 2 layer boards.

The board pretty much has to be 2 layer to keep it affordable for regular hobbyists. A 50+ square inch 4 layer PCB would cost *much* more and basically make it impractical. As far as I know the only versions of these boards were built in laboratories one at a time by students using wire wrap.

I think the design is fairly solid since I've contacted the author and the known errata is fairly minor. Of course, the whole point of the project is to get it working so I would expect some latent defects in the design package. That's normal and part of the build and test phase to find and fix those problems.

This project is still closer to the beginning than the end. I've got the book and made the schematic and PCB layout but there is a LONG ways to go before this is done!

Thanks and have a nice day!

Andrew Lynch

PS, when I started the board in the autorouter, the initial solution was 503 vias and more than 1300 inches of overall trace length. After less than 24 hours it is already down to 322 vias and 1253 inches overall trace length so it is really wiping up all the unnecessary artifacts of the initial solution. The PCB layout you see on the wiki is just after it solved initially so it is the worst possible case.
 
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lynchaj said:
I am thinking the original boards were only wire wrap units since the density certainly is pushing 2 layer PCB component density.
Click to expand...

Oh right I see, it probably was meant for wire wrap. However, a good wire wrap board would have had large ground zones on top and Vcc zones on the back which would keep the daisy chaining to a minimum. As you say, use plenty of decoupling caps.

The board pretty much has to be 2 layer to keep it affordable for regular hobbyists. A 50+ square inch 4 layer PCB would cost *much* more and basically make it impractical.
Click to expand...
Yes I see the issue for us hobbyists. Too bad, as a 6 layer board (4 signal layers and internal ground and voltage planes) would be sweet for this application.

I think the design is fairly solid since I've contacted the author and the known errata is fairly minor.
Click to expand...
Yes it looks good although I am still trying to understand the /DTACK logic.
Good luck on an interesting project. The 68000 was a great chip.
-Dave
 
Hi! Just for curiosity I checked on the prices for a 4 layer PCB of comparable size. The tooling fee triples and the per unit board cost more than doubles. Since the tooling fee represents a considerable portion of the final cost per board plus shipping, etc, I am guessing that a 4 layer PCB would triple the price over a 2 layer PCB. I didn't ask about the 6 layer board but it is probably in the same neighborhood scaled up. Expensive!

Thanks and have a nice day!

Andrew Lynch
 
Hi! Work continues on the S-100 68K CPU board project. Here is a 3D rendering of the PCB so far. Trace routing is underway. I have no idea when it will be complete. My plan is to make a few prototype PCBs and send them to some builders for the first round of build and test. Obviously they are going have to be experienced with 68K systems.

Still looking for volunteers to compare the schematic against the book for accuracy. I've done it myself several times and found many little things. The more eyes going over the project catching the little "gotchas" the better. It is a complicated board with lots of opportunity for errors! The more the merrier!

Thanks and have a nice day!

Andrew Lynch

View attachment 4599
 
Hi! The S-100 68K CPU board continues chugging away in the trace routing optimizer. I suspect it will be there for quite a while. I've done some checks and will do a final check soon to make sure the schematics match up properly. From then its let it finish in the trace routing optimizer and get some prototype PCBs.

Just as a rough idea, who would be interested in the S-100 68K CPU board build and test phase? You can bet the first round boards will have problems so expect to do hardware and software debugging. Depending on how many are interested will determine what sort and how many prototype boards I'll order. I know of a few for certain and maybe others. Please let me know. This phase of the project is intended for experienced 68K hardware and software experts.

My plan is to cover the first round of prototype boards but if you want to chip (optional) in they are about $30 each.

Thanks and have a nice day!

Andrew Lynch
 
Hi! Here is a quick update on the S-100 68K CPU board project. The schematic and PCB layout have been checked and rechecked several times and the PCB design has completed enough of the trace route optimization to get some prototype PCB boards made. I've ordered a small number of S-100 68K CPU boards for the small group of initial build and test team which should get underway in about three weeks or so. I have no idea how long that is going to take since it depends on what we find in initial build and test phase. I will keep you posted occasionally on our progress. There is no estimate for availability of manufactured PCBs although if you want to be put on the waiting list please let me know.

Thanks and have a nice day!

Andrew Lynch
 
Hi
Update to the S-100 68K CPU project. Second iteration prototype board has arrived and sent to build and test team. The original design was basically sound and required only minor updates for full functionality. However there were a couple of obsolete parts to replace. Replaced onboard tiny SRAMs with a UART for local serial connection. Updated 27128 EPROMs with Flash memory chips. Replaced DIP-64 CPU with PLCC-68. Added a few pull up resistors so CPU could come up independently as bus master.

Overall new board should be much better. The plan is the updated design will be near final pending the results of this build and test.

Thanks

Andrew Lynch
 
Yes the final S-100 68K board has been done a few weeks ago (currently working on a 80386!). Andrew has had it being optimized in terms of board traces etc. It is a complex board and as I understand the program was running very slow. I think Andrew felt it was now as good as it is going to get as is about to order a batch. I will let him update that status
John M.
 
Hi!

I think the next releases will be the S-100 LAVA and S-100 68K CPU board PCBs. Then I'll do some PCB reorders like the S-100 SMB and then the S-100 bus extenders. Things are progressing a bit slower than I've hoped but still moving along. Also took a couple of detours which added some time too :)

The good news is all the S-100 backplanes have gone to their builders and only two of the S-100 Serial IO board PCBs remain. That's a relief!

Thanks and have a nice day!

Andrew Lynch
 
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