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Proper Method of Triggering S-100 Interrupts

glitch

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I'm working on adding a debounced switch to my S-100 board for triggering /INT and /NMI during debugging and prototyping. Right now, I have a TTL gate driving /NMI, but it seems to me that anything else trying to drive the line would have to fight the gate to lower the line. That's probably not an issue since it'd be sinking rather than sourcing. Would it be more appropriate to drive the line with a tristate buffer gate? One like the 74LS367 would allow me to either drive the line low or deselect the buffer and put the line in Hi-Z.
 
Glitch on the S-100 Bus both the /NMI and all 8 /INT's must be driven low by Open Collector outputs (eg a 7406). This is because any board can pull the lines low. If you use a totom pole TTL gate you will potentially burn out the gate with two gates pulling against each other.
Use two 74LS00's cross connected to debounce the 7406 input.
 
A diode in series with a pushbutton to ground with a debouncing cap across it will get the job done. Or just put a diode in series with the output of your TTL gate to pull the line down.
 
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Great information! Exactly what I was looking for! I figured there would be at least contention, if not outright device failure, over driving the line with a TTL gate. I hadn't thought about open collector devices, but that makes perfect sense. I have a pile of 74LS05 devices and may use one there -- the signal gets inverted from the debounce circuit to the correct polarity anyway, since the debounce circuit is really driving a 8212 8-bit latch's STROBE pin.

I went with a 555 in monostable mode for switch debounce, since it gets the job done and also gave me an excuse to use one of my TO-5 metal can 555s! Don't know why, but I like the look of metal can packages.
 
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