So if you really want to be thorough, you'll have to duplicate that functionality at least at a register level.
I'm afraid it can be more difficult than whole XT I made until now...
So if you really want to be thorough, you'll have to duplicate that functionality at least at a register level.
You can probably do a cycle-accurate 8088, since it's effectively divided into two sections that work independently, and the timings for both sections are known (4 clock cycles per byte to read a byte into the prefetch queue, and the instruction timings apply after the instruction is fully in the queue).
Cool project! It is interesting to see a combination of the 8088 and an FPGA. Any reasons for not implementing 8284 and 8288 in FPGA as well?
It must be more complicated than that, because not all instructions fit in the queue! I have a (much neglected) project in progress to figure out the timings for a cycle-exact 8088 emulator.
It must be more complicated than that, because not all instructions fit in the queue! I have a (much neglected) project in progress to figure out the timings for a cycle-exact 8088 emulator.
So even MESS doesn't have one?
Is cycle exact emulation of the 8086 easier?
Are there programs that cannot run on any of the existing emulators or do they just not run at the proper speed?
I'm not aware of any programs that have been published and for which the consequences for running without cycle exact timing are anything except running at the wrong speed. I expect that to change in the next couple of months.
It must be more complicated than that, because not all instructions fit in the queue! I have a (much neglected) project in progress to figure out the timings for a cycle-exact 8088 emulator.
(my guess is using NOPs or JMPs to drain the queue).
You two hush now!
In a month or so, new software will be published that will not work 100% correctly on any emulator.
I suppose the only ways to get perfect cycle emulation is to a) look at the original RTL, or b) run a real 8086/88 along-side an FPGA implementation in lock-step through a significant amount of the code ever written for the 86/88 and stop the clock when the BIUs don't match. Now that would be an interesting project.
Guys, what about my original question about virtual FDD ?
I would very appreciate if someone with real PC or PC XT (most important - 8088 CPU required) can try to run Paratrooper
Hello, this is a very intersting thing. But on the other side, why not use the MIST FPGA platform?