The PC uses the 8088 in “Maximum Mode”, which means the minimum-mode /HOLD line turns into /RQ. The datasheet explains how to use it; the TL;DR is using this mechanism correctly would basically let you have the two CPUs wired up in parallel, but using it is more complicated than just putting a toggle switch between them and holding this line down, you’d need a small state machine to send the correct sequence to the “spare” CPU to sleep it on startup. This same pin is used by the DMA controller so whatever you stick in there also needs to pass through its activity to the right CPU.
The DMA controller on the PC and XT doesn't use RQ/GT protocol... Instead, when there's a DMA request, the wait logic generates wait states, isolates the CPU from the bus, and lets the DMA do its business.
Some clones, particularly chipset based ones, such as FE2010A, PT8010AF, 82C100 do use RQ/GT protocol for DMA.
I don't exactly know that's the purpose of this project and at how the CPU switchover is going to be controlled.
It will be difficult to have both CPUs running.
It also will be difficult to switch the CPUs on the fly: the CPUs have their internal state - registers and instruction queue that would need to be synchronized somehow.
For example:
- A predefined memory location to store all the registers
- Hardware to switch between CPUs, e.g., an I/O port that will select the active CPU and reset the CPU on demand
- BIOS modifications or a TSR to store the state and initiate the switchover
- BIOS modifications to POST that instead of booting the system will initialize the CPU with the stored state
If the goal is to simply switch between CPUs while the computer is powered off, putting some buffers/transceiver on most I/O signals should be enough. It is not a good practice to drive pins while the power is disconnected. In the best case it wouldn't work, in the worst - will damage the ICs.