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8272 FDC to 8" drive connections

I spent an interesting afternoon, the football was rather boring. I set up with the drive upside down so that I could gain access to the drive's TP's and chips. I was completely wrong about the signal not going low enough or the 7438 not being able to pull the level low enough. That was working fine, apparently I must have been monitoring something incorrectly. There is a test point on the Shugart drive TP27, which is the output of essentially the AND of the step pulse and DS0. I was getting pulses here. There were 8 us pulses 12 ms apart, which is what I have SRT set at. I compared these pulses with DS0 grounded and connected to the ribbon cable. There was no difference in the waveform. So something else was making the difference between grounded and not grounded. There are two D flip flops that generate the step motor pulses. Here again I monitored the outputs both with the DS0 grounded and not grounded, again no difference. Next I moved the scope to the outputs of the three input NANDS, which are the beginning of the drivers to the stepper motor. Here there was a BIG difference. One of the inputs of the 3 input nand comes from the Head Load through a jumper called HL. Here. if you have a circuit diagram, I had jumpers DS1, A, B, X, & HL closed. This provided a path from the device select to the 3 input nands, For some reason this signal was blocking the 3 input nands from operating the step transistors. I'm still not exactly sure why this caused this problem, but with the HL jumper removed, the RECAL command works as it should. The HL jumper is supposed to be in place according to the SA800 manual, but for some reason it caused a problem. Do you think I solved this or just band aided it? I think I'm going to move on and code the seek command and see what happens. Thanks Mike.
 
Set your drive jumpers up according to Section 7.3 of the Shugart SA800 manual. You want to step without loading the head. This is what the 765 expects. As noted, the 765 can overlap seeks on up to 4 drives. Moving the heads without the door closed or disk inserted doesn't hurt a thing--and in this case, it's necessary.
 
Today, I wrote some code for the SEEK command. I got this to work, but for some reason I was not getting an interrupt when the SEEK command completed. The head would move but no interrupt. Turns out I had written the wrong code for the 8259 End Of Interrupt. I got confused between specific and non specific, etc. I had sent out the wrong word and even to the wrong address. After changing this to the correct values, SEEK command would go to any track that I would input.

One thing I have to look at or add to my code is the interrupts, when to enable and disable AND the interrupts that are generated when the drive ready changes. Currently I disable all interrupts at the beginning of the initialization and don't turn them on until I'm waiting for an interrupt in the execution phase. But I could get a ready change at any time. I suppose that I should add some code to check ST0 bits 5, 6 & 7. Then I suspect that I need a couple Drive Ready Flags. If a drive is not ready should I suspend sending commands to that drive? Also when exactly should I disable/enable the interrupts or shouldn't I at all?

Thanks Mike
 
Seek commands can be executed on a not-ready drive, so the answer is "sometimes". On a PC, the 765 has the READY line tied high, with the result that a read or write on a not-ready drive hangs the FDC. The PC gets around that by having a deadman timer on command execution. If it elapses, the FDC is hard-reset. But that's not your case.

Here's what I do and I've not found any obvious problems with this scheme in many years.

The problem with the CPU enable-disable interrupt instructions is that they're a shotgun approach. If you have a device (say a timer) or a keyboard) you're going to run into grief sooner or later. The better approach is to disable interrupts only in the case where you really need to use several instructions to perform an atomic operation--that means that interrupts are disabled only for a few microseconds at most.

However, it's not a bad policy to use the 8259 to mask interrupts that you're not expecting. So, in this case, you don't unmask the FDC interrupt until just before you issue an FDC command that will result in an interrupt--and then mask the interrupt again in your ISR. That way, you keep a tight fence on specific interrupts. It makes life much easier.
 
That makes sense. I only use IR1 interrupt, this one is for the FDC. Everything else is polled. I've used the mask to block all the interrupts except IR1. Then I've been using EI and DI. I have a short Interrupt Service Routine where I disable interrupts, set an Interrupt Flag, do an End Of Interrupt, enable interrupts and return, Very short. Then when the command phase is over I jump to a wait for interrupt routine. Basically It's a loop that watches the interrupt flag. Later I'll add a timer so that it doesn't hang here. Once the interrupt occurs I jump out of the loop, check what command was issued and finish the command. The part that I have not coded for is the ready change. I can check ST0 during a SIS, so far I have assumed that each command has terminated properly. I can also keep track of drive ready status. I've just read the 765 app notes and I see that there are some general flowcharts. Looks like the only time the interrupts are disabled are when the command is being issued. I'm going to take some time and clean up and organize this code. Seems to be piling up. This is going to be larger that I had first thought, but as long as it works. Thanks Mike
 
Today, I installed some code for my 8080 machine to have the 8272 FDC read a sector from the Shugart 800 8" drive. Previously I have successfully written code for the Specify, Sense Drive, Sense Interrupt, Recalibrate and Seek commands. All these commands have been tested and seem to work. By that I mean I can not find any reported errors after they are run. My test read code sets the drive to 00, the track to 00, and the sector to 1. The DMA is set for a write (I/O to Memory), the terminal count is set for 128 bytes and the DMA address was set to a spot in memory. My specify command was set for DMA control and had reasonable times set. The command phase of the read had all nine commands.
1st command MT=0, MFM=0, SK=0, Command = 006 (Octal)
2nd command HDS=0 DS12=00 Command = 000
3rd command Cylinder = 000
4th command Head = 000
5th command Sector = 001
6th command N (sector size code) = 000
7th command EOT = 032
8th command GPL = 007
9th command DTL = 200

I'm confident that the FDC accepted these commands, because after they are issued, the drive is selected (active light is on) and the head loads. Right after the 8080 software issues the 9th command, it enters a loop waiting for an interrupt. This is where I get stuck. This means that the read command went through the command phase and entered the execution phase, but never issues an interrupt that indicates the end of the execution phase.

The fact that the drive was selected and the head loaded means that the execution phase started. The FDC should load the head and wait the head load time, then start reading the ID's. I think, according to the 8272 notes, two things can happen. The FDC will find the track/sector and issue a DMA request or if it can not find the track/sector and if two index marks are seen, the read command is terminated.

Last winter I tested the DMA circuitry and I know that it works. I connected my scope to the DRQ line of the 8272 and I never see a pulse. The notes say that I should see a 6 usec low to high pulse here. I tried looking for the pulse many times but I never seen it. The 8080 never went into a hold, another indication that the DMA request was not issued. I don't know this for fact, but I figure that if the FDC doesn't read or can't find the data, it most likely will not make a DMA Request. So if this is the case, then the read command should be terminated after two index pulses are seen. I checked the index pulses and they are there. The notes don't specifically state this, but I would assume that if the read is terminated an interrupt should be issued and then I could sense the interrupt with an SIS command and check ST0 for errors, but no interrupt.

I have to do more investigation, but would appreciate any suggestions. Thanks Mike.
 
For some reason I have, at least I think, is a goofy pulse on both the index and ready lines. At first glance the index pulse looked like a normal high signal with short low pulses, every 167 msec. But, zooming in on the short low pulse, it is actually two low pulses.

-- ------- -------
| | | |
------ -

The signal goes low for 15 usec then high for 15 usec and another 2 usec low pulse. I think that the second low pulse should not be there.

The ready pulse is the same, except it occurs ever 1 msec.

The index pulse at the Shugart TP10 and TP12 points do not have the extra pulse and are actually low pulses that are 1.1 msec wide, ever 167 msec.

The device select line 0 is supplying the extra pulse.

Looking at the other DS lines, DS1 has just a 15 used low pulse. DS2 has a 14 usec low pulse, DS3 is mostly low with 46 usec high pulses, every 1.1 msec.

I moved back to the 74139, 2 to 4 line decoder and looked at the inputs. It appears that the 8272 is supplying waveforms that are causing the extra pulse on DS0.

DS1 8272 Pin 28 is mostly high with 32 usec low pulses every 1 msec.

DS0 8272 Pin 29 is mostly high with two 15 usec low pulses that are within the low of DS1.

The problem is at the start of the pulses DS0 and DS1 are both low for 15 usec which causes the 74139 to lower Output 0 for 15 usec. Then DS0 goes high for 15 usec. The 74139 then lowers Output 1. Then DS0 goes low again, BUT DS1 is still low for another 2 usec. This causes the 74139 to output 0 again for the 2 usec.

Now I'm thinking what could cause the 8272 to output odd DS0 and DS1 pulses? Is the 8 Mc clock OK? I have a 8224 with a 8 Mc crystal driving the 8272 pin 19 from the OSC output. I looked at the clock signal with my scope and the period looks like the frequency is 8 Mc, but this is near the limits of my scope. What concerns me is that the signal is not a square wave. It looks like a saw tooth and part of the signal is negative. Shouldn't this be a square wave. All my documentation on the 8224 doesn't talk about the OSC output and has no pictures.

I'm wondering if I should use a different oscillator, or is there something else wrong. Mike
 
Mike_Z said:
For some reason I have, at least I think, is a goofy pulse on both the index and ready lines. At first glance the index pulse looked like a normal high signal with short low pulses, every 167 msec. But, zooming in on the short low pulse, it is actually two low pulses.

-- ------- -------
| | | |
------ -

The signal goes low for 15 usec then high for 15 usec and another 2 usec low pulse. I think that the second low pulse should not be there.

The ready pulse is the same, except it occurs ever 1 msec.

The index pulse at the Shugart TP10 and TP12 points do not have the extra pulse and are actually low pulses that are 1.1 msec wide, ever 167 msec.

The device select line 0 is supplying the extra pulse.

Looking at the other DS lines, DS1 has just a 15 used low pulse. DS2 has a 14 usec low pulse, DS3 is mostly low with 46 usec high pulses, every 1.1 msec.

I moved back to the 74139, 2 to 4 line decoder and looked at the inputs. It appears that the 8272 is supplying waveforms that are causing the extra pulse on DS0.

DS1 8272 Pin 28 is mostly high with 32 usec low pulses every 1 msec.

DS0 8272 Pin 29 is mostly high with two 15 usec low pulses that are within the low of DS1.

The problem is at the start of the pulses DS0 and DS1 are both low for 15 usec which causes the 74139 to lower Output 0 for 15 usec. Then DS0 goes high for 15 usec. The 74139 then lowers Output 1. Then DS0 goes low again, BUT DS1 is still low for another 2 usec. This causes the 74139 to output 0 again for the 2 usec.

Now I'm thinking what could cause the 8272 to output odd DS0 and DS1 pulses? Is the 8 Mc clock OK? I have a 8224 with a 8 Mc crystal driving the 8272 pin 19 from the OSC output. I looked at the clock signal with my scope and the period looks like the frequency is 8 Mc, but this is near the limits of my scope. What concerns me is that the signal is not a square wave. It looks like a saw tooth and part of the signal is negative. Shouldn't this be a square wave. All my documentation on the 8224 doesn't talk about the OSC output and has no pictures.

I'm wondering if I should use a different oscillator, or is there something else wrong. Mike
Click to expand...

Given that none of the vendors want to talk about what the OSC output of the 8224/74LS424 really looks like, only that it has the period of the crystal, I wouldn't assume a square wave output, much less a 50% duty cycle. For the day, 8MHz was quite a high frequency. DIP oscillators are cheap and have a known output.
 
Obviously the DS0 and DS1 of the 8272 must be derived from the this clock signal. The 8272 notes say the signal must be 8 Mc with a 50% duty cycle. My 8224 OSC output is not 50%. I could attempt to square up the signal, but I don't think that there will be a 50% duty cycle. The fact that I believe I have a timing problem affecting the device select lines, I think the 50% duty maybe the trouble. I suppose that I should look for a better oscillator. Mike
 
You could certainly use the output of a DIP packaged oscillator to do the job. If you wanted to drive 5.25" DD drives, you could simply swap that out for a 4MHz unit.
 
I've been looking even closer and checked the 4 Mc signal from the 7476 divider, even there the signal is deformed, better but still rather curvy. I've spent some time looking for a clock generator, specifically 8 Mc 5 volt something in a DIP package with a square wave output. Been looking at a bunch of stuff, but have not found anything that looks good. You mentioned a DIP package oscillator. I saw a couple of those on eBay. Thought that one of those would be nice, but I could not find any documentation on them. Got any sources?

I also found an old study made by TI, AN-400. It's about low power crystal oscillators. Here they have some empirical data about Pierce Oscillators, using CMOS inverters and just a single transistor. These also look good, but there is no information about the outputs. I would think that the inverter circuit probably supplies a square wave output, but the transistor would be more of a sin wave and would require conversion, probably would need some inverters anyway.

Since I'm only driving two chips, the 8272 and the 7476 divider, I'm thinking that the inverter circuit may be the ticket. I'm going to slap together a circuit and see what comes of it. Let you know. Mike
 
The output from a flip-flop driven by any sort of signal should be a clean 50% duty cycle square wave.

I wonder if what you're seeing on your scope is right. But yes, the archetypal TTL oscillator is a 7404 inverter, biased into its linear region. For example consider this. The usual think that follows is fllip-flop (e.g. 74LS109) to reduce loading and ensure a 50% square wave output (so, for 8 MHz, you'd use a 16MHz crystal).

When I'm prototyping, unless a discrete crystal is recommended, I'll use a packaged XCO. I just don't need to worry about the circuit. XCOs are plentiful and inexpensive. here's an example.
 
You know, I've been trying to get something to oscillate all morning. When you don't want something to oscillate, like a power regulator they will sing like birds. I ordered one of those oscillators you pointed to on eBay. I'm sure it will show up in a few days and then maybe I can get going again. Thanks much Mike.
 
While I'm waiting for the 'canned' DIP oscillators. I've been playing with the ic & discrete oscillators. After some horsing around I got them to oscillate, but it is rather tricky. Seems that the capacitance is very critical. Just a few pf difference made the circuit work or not. I'm guessing that the capacitance and resistance, both actual part values and hidden vales of the amplifier and crystal contribute to getting 360º phase shift around the loop. Being off even a little will affect how quickly the circuit will oscillate. I had better success with using a 2N3904 transistor, apparently I had more control of the external values, it started up much easier. BUT, then I had more of a sine wave that would need conditioning. I'd continue with this, but I have limited space on my S-100 board for the extra stuff and I'm not sure it will continue to work in the new environment. I ordered some 'canned' units and it will take the place of the 8224 clock chip, not needing any additional space. Hoping to get the new stuff next week some time. Mike
 
I have an 8080 CPU. The 8224 clock that I'm replacing is the FDC clock. I'm running the CPU 8224 at 18.432 Mc, but the FDC clock needs 8.0 Mc. I suppose I could have used one of my timers for counting down, but I want those for other things. Sorry for the confusion. Mike
 
I've been thinking about why I never got an interrupt after a faulty completion of a read command. The application notes clearly states that if the index mark is detected twice before the sector ID is found, the "sector not found error" is set, and the read command is terminated. The interrupt code is set to Abnormal termination. I'm pretty sure that with the double index mark I was getting from the bad 8.0 Mc clock waveform was causing the read command to improperly terminate. I was expecting an interrupt, but never got one. The application notes does not say whether an interrupt is issued or not. I suspect it does not, not really sure. So I think that in my WAITINT, wait for interrupt routine, I'll wait 100 milli seconds for an interrupt and then if one doesn't show up, I'll do a sense interrupt and see if an abnormal termination occurred to finish things off. Mike
 
Well.... while I'm waiting for a WD9216 PLL to show up in the mail, I thought I'd do a little checking prior to installing it on my 8272 FDC board. I wanted to see if I could get the FDD head to load and see if anything at all would come out of the heads. Well, there is, but not what I had expected. I get read pulses even when the head is not loaded. I get groups of pulses every msec or so. This is not good. After some nosing around I found that it is coming from the 8080 machine. The pulses are not there when the 50 wire ribbon cable is disconnected. I get the pulses even when the 8080 is stopped in a wait state. If the 8080 is turned off there are no pulses. Then next task was to attempt to isolate the problem to a particular wire on the 50 wire cable. Turns out, it's the device select line DS0. So I tried to connecting the FDD as DS1, DS2 and DS3, all produce the same problem. I connected the scope to the DS0 line and there seems to be some negative transitions that correspond with the stray read pulse. The 8272 is constantly polling each drive for a ready state change. Each DS line is normally HIGH and for a few usec there is a low pulse which is the poll. On the HIGH to LOW transition there is (sometimes, probably more than 50%) a negative pulse. The transition will go from +4 volts to maybe -1.5 volts and immediately return to about +0.2 volts. This spike is only on the HIGH to LOW transitions.
The DS line out of the 8272 are decoded by a 74LS139 then are conditioned by a 74LS04 and a 74LS38 before connecting to the 50 wire ribbon cable. The ribbon is about 5 feet long. The DS0 line on the Shugart 800 drive has a 150 ohm pull up and connects to a 7428 chip.
I'm not sure that the negative pulses are causing the read pulses, but they do seem to correspond. I tried a different 74LS38 open collector NAND chip, but that didn't make a difference. I tried an addition ground between the FDC board and the FDD, no change. I thought that maybe the inductance of the ribbon could be causing this negative spike. The 5 volt regulator on the FDC board is not oscillating. I haven't checked the FDD power. I have thought of changing the 74LS38 chip to a 7438 chip because the later output current capability is 10 times higher. Maybe another type of line driver should be used. Anyway, these stray read pulses have to be removed. I can not image how it would work with them. Any suggestions or thoughts. I appreciate the help, thanks, Mike.
 
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