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8284A suitable to drive a 6502?

Mike Chambers

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the 6502 needs a clean square wave to drive it, and i was wondering if the 8284A can put out a suitable signal for it. i believe the 6502 needs a 50% duty cycle, but does this actually matter? there seem to be three outputs from the 8284A that give some sort of clock signal.

if i put a 1 MHz xtal on X1 and X2 (and tie a few lines as necessary) does the 8284A turn it into a proper square wave? and do i have these outputs correct:

1 MHz into X1/X2:
OSC = 1 MHz 50% duty square wave
CLK = 1 MHz 1/3 duty square wave
PCLK = 1 MHz 1/6 duty square wave

i know OSC is meant to drive other 8284A chips, so does it actually send out a clean square on that pin or is it a direct connection to the xtal? either i am bad at reading, or the datasheet isn't clear on much of this. i am willing to entertain both possibilities.

if i'm wrong, and the 8284A won't do the job for a 6502, what is the simplest circuit i can build to make a good driving signal? so many of you guys are great with EE-type stuff. thanks! :)
 

modem7

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i believe the 6502 needs a 50% duty cycle, but does this actually matter?
On the Internet is, "Note that the 6502 and 65816 processors prefer a 50% duty-cycle clock" (with the 'prefer' bolded).
If it's true, there may be implications of using something other than 50%. Hopefully someone with knowledge about that will answer.

and do i have these outputs correct:

1 MHz into X1/X2:
OSC = 1 MHz 50% duty square wave
CLK = 1 MHz 1/3 duty square wave
PCLK = 1 MHz 1/6 duty square wave
From the NEC uPB8284A datasheet:

"The frequency of CLK is one third of the crystal or EFI frequency"

"For driving the MOS output level, there is a 33% duty cycle MOS output (CLK) for the microprocessor, and a TTL output (PCLK) with a 50% duty cycle for use as a peripheral clock signal. This clock is at one-half of the processor clock speed."

In reference to OSC, "This TTL level clock is the output of the oscillator circuit running at the crystal frequency."

Summary:
OSC = Crystal frequency , ??? duty cycle , TTL output levels
CLK = OSC/3 , square wave , 33% duty cycle , MOS output levels
PCLK = CLK/2 , square wave , 50% duty cycle , TTL output levels

i know OSC is meant to drive other 8284A chips, so does it actually send out a clean square on that pin or is it a direct connection to the xtal?
Unlikely to be direct because of loading effects. A block diagram in the uPB8284A datasheet shows an inverter being used. That would take any signal to the "TTL output" levels and square it.
 

Mike Chambers

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On the Internet is, "Note that the 6502 and 65816 processors prefer a 50% duty-cycle clock" (with the 'prefer' bolded).
If it's true, there may be implications of using something other than 50%. Hopefully someone with knowledge about that will answer.


From the NEC uPB8284A datasheet:

"The frequency of CLK is one third of the crystal or EFI frequency"

"For driving the MOS output level, there is a 33% duty cycle MOS output (CLK) for the microprocessor, and a TTL output (PCLK) with a 50% duty cycle for use as a peripheral clock signal. This clock is at one-half of the processor clock speed."

In reference to OSC, "This TTL level clock is the output of the oscillator circuit running at the crystal frequency."

Summary:
OSC = Crystal frequency , ??? duty cycle , TTL output levels
CLK = OSC/3 , square wave , 33% duty cycle , MOS output levels
PCLK = CLK/2 , square wave , 50% duty cycle , TTL output levels


Unlikely to be direct because of loading effects. A block diagram in the uPB8284A datasheet shows an inverter being used. That would take any signal to the "TTL output" levels and square it.

ah, yes the PCLK seems to be driving it fine, but it's running at 167 KHz - ouch lol.
 

Mike Chambers

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What's wrong with a 2MHz XCO driving a flip-flop? 50% duty cycle, pretty much by definition and non-overlapping.

i'm not that experienced with this sort of thing, do you mean like connecting the crystal to an inverter or a latch?
 

Chuck(G)

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You can generate the fundamental frequency any way you want--I prefer XCOs (packaged oscillators) because there aren't any timing-critical external components. Drive a J-K flip-flop with the J and K inputs tied together to form a T flip-flop (you can also use a D flip-flop with the D input connected to the Q/ output, so it toggles every clock). Your outputs are the Q and Q/ at exactly one-half the input frequency. No need for a fancy clock chip.

If you need serial I/O and need a baud-rate source for the UART, you can even use an 1.8432 MHz XCO (readily available) to serve as baud-rate clock source and run the 6502 at 921 KHz, which is pretty close to the 1MHz you're after.
 

Mike Chambers

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ok, thanks. i'll not be adding serial, i've designed a parallel interface for it. you can see it work here, sending output to an old laptop using nibble mode.


that laptop has seen better days.
 

Mike Chambers

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i'm making a video circuit based on a motorola 6845, and will be using a monochrome monitor. according to the pinout specs for video cable, the horiz sync is negative 5 VDC. the hsync output pin on the 6845 is positive 5 VDC. i do have a neg. 5 VDC line coming out of my power supply, but how should i get that to go into the monitor's hsync pin when the 6845's pin goes active (high)?

probably a dumb question, but is it possible to use a 74LS08 AND gate by routing the 6845's hsync pin to both inputs of a gate, and put the circuit ground on the LS08's Vcc line and the -5 VDC line on it's ground or something similar? or, am i going to have to build a special circuit to directly invert the hsync signal?
 

MikeS

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i'm making a video circuit based on a motorola 6845, and will be using a monochrome monitor. according to the pinout specs for video cable, the horiz sync is negative 5 VDC. the hsync output pin on the 6845 is positive 5 VDC.
Are you sure it's really a -5V pulse, and not a negative-going pulse on a +5V line?
 

Mike Chambers

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Are you sure it's really a -5V pulse, and not a negative-going pulse on a +5V line?

hmm, well i just found a PDF of the XT tech reference and it says this:

Video Signal: Maximum bandwidth of 16.257 MHz.
Vertical Drive: Screen refreshed at 50 Hz with 350 lines of vertical resolution and 720 lines of horizontal resolution.
Horizontal Drive: Positive-level, TTLcompatibility at a frequency of 18.432 kHz.

so, yeah i guess it looks like i'm okay then! awesome.

EDIT: i spoke too soon, it appears the vsync needs to be negative according to this pinout i just found. the tech ref doesn't specify for that one.

Code:
Pin 	Name 	Description
1	GND	Ground
2	-	-
3	-	-
4	-	-
5	-	-
6	I	Intensity
7	VID	Video
8	HSYNC	Horizontal Sync TTL Positive
9	VSYNC	Vertical Sync TTL Negative

so, i guess my original question still stands. :confused:
 

Mike Chambers

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okay, i think i've figured out a way to do this. if i invert the output of the 6845's VSYNC pin so that when it goes high it turns into low, then run that into both inputs of an AND gate who's Vcc is the circuit's ground and the gate's ground is wired into the power supply's -5 VDC. this won't set my house on fire will it?
 

Chuck(G)

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You're making things too hard. Remember that sync and video are AC-coupled signals--the DC level doesn't really matter. So some capacitive coupling will have the same effect.
 

Mike Chambers

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ah, i didn't realize that. still learning about all this crazy hardware stuff. that 8088 project i tried doing last year ended up failing, so i thought i'd try again with the 6502. great results so far. i will probably hold off on finishing the video circuit until i finish my monitor firmware, which is coming along well. i even added support for downloading binary data directly into RAM via a PC's parallel port to run arbitrary code without having to burn new data onto EEPROMs all the time.

speaking of the parallel port, the method of data transfer i'm using to go from the breadboard to the PC seems to only work on one computer i own.. an old 486 canon notejet. the PC side of course sends out data a byte at a time using the regular data lines, for the breadboard's output i'm using the 5 parallel lines that show up as the high 5 bits of the status register to send 4-bit nibbles, with the highest bit indicating if the data currently in the register is the low or high nibble of a byte.

while it works on that laptop, every other machine i've tried (like 3 or 4 of them) the "select" line always shows up as a 0 in status bit 4, whether i've got the line high or not. any ideas? i wouldn't care since it works on the canon, but soon i'd like to set up a way for me to telnet into it and since the laptop's parallel port is being used by the breadboard interface, i can't stick my xircom PE3 on it at the same time.
 

MikeS

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I think you'll find that TTL means between 0 and +5V and just like positive and negative logic, positive and negative refer to the 'direction' of the pulse from the resting state, i.e. a normally 0V signal that has positive pulses going to +5V, or a normally +5V signal with negative pulses going to 0V.

But if you really wanted to convert a +5V pulse to a -5V pulse the simplest way is often an opto-isolator; your way won't work because aside from exceeding the respective voltage limits the input to the gate will always be high or even higher, i.e. never below the gate's Vcc.

But yes, as Chuck wrote while I was typing in the end it's an AC-coupled signal, so it's not really an issue.
 
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nige the hippy

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opto isolators are sometimes (but not always) a bit slow.

easiest composite video...
get a couple of e.g. 2k7 resistors one to 5V the other to ground to get a 2.5V middle (that'll change but don't worry)
feed the positive going Hsync pulses into (a spare inverter + a diode pointing in to it) / (an open collector inverter) or (the gate of a logic-level mosfet with the source connected to gnd) i.e something that will pull down when a positive pulse goes into it.
do the same with the Vsync
feed the video signal into a variable resistor or a resistor of about 2k7 ish
Join all the outputs together & bung it through a 0.1uF cap

Oh..... Here's a quick diagram - no guarantees as straight off the top of my head & its been a while, so open to comment!

Values might need tweaking


View attachment video cct.pdf
 
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