glitch
Veteran Member
In remembrance of Chuck Peddle, this year's VCF East overall theme is going to be the 6502 processor. I didn't want to do "just another 6502 SBC," since there are plenty of great options out there, so I decided to do something that's still 6502 at its...core 
I designed a single-board computer around the Rockwell R6501Q, which is an enhanced 6502 core in a 64-pin QUIP (QUad Inline Package) with built-in RAM, serial port, counters/timers, and parallel I/O. This CPU is more often seen in embedded applications from the 80s and 90s.
Design on the R6501Q SBC started in early February, but there have been delays in prototype manufacturing due to the coronavirus outbreak in China. I finally got the prototype circuit boards in today, and it's a go! Pictures:
This is the first prototype assembled. Specs:
* Rockwell R6501Q CPU at 1 MHz (supports R6501AQ at 2 MHz)
* 32KB ROM in 4K segments
* 32KB static RAM
* Onboard serial port
* Two 8-bit parallel ports brought out to headers
* Onboard counter/timer available
* Glitchbus expansion connector
Here's a closeup of the CPU:
The sockets for QUIP-64 packages are difficult to find, and the suppliers that claim to have them want a lot of money for them (the only one that returned my RFQ wanted $18/ea QTY 100). I decided to just use Aries machine pin SIP socket strips. Alignment isn't too difficult, but it's a bit fiddly to get the CPU aligned and inserted. On extraction, the outer pins want to bend, with the 90-degree bends in them becoming two 45-degree bends. One of my R6501Q CPUs had bent pins and, rather than fight it into a socket, I just soldered it to the board.
The SBC is expandable via Glitchbus, the 8-bit bus I designed to be processor-agnostic and first implemented with the 8085 SBC rev 3. When onboard memory and I/O devices are not being accessed, the Glitchbus is active. Since the R6501Q, like the 6502, doesn't have a separate I/O space, I dedicated the 256-byte page at 0xEF00 as the I/O page: accesses to that page pull the BIO**M line high to indicate that an I/O transfer is taking place. Here, the prototype R6501Q SBC is being tested with an 8255 PPI Glitchbus board:
Works fine!
Check this thread for more updates on the development progress. Big thanks to TangentDelta for customizing the eWoz ROM monitor for the R6501Q SBC, it helped a ton in quickly testing the prototype!
Please fill out the survey *especially* if you're going to be at VCF East 2020 and want to build this board!
I designed a single-board computer around the Rockwell R6501Q, which is an enhanced 6502 core in a 64-pin QUIP (QUad Inline Package) with built-in RAM, serial port, counters/timers, and parallel I/O. This CPU is more often seen in embedded applications from the 80s and 90s.Design on the R6501Q SBC started in early February, but there have been delays in prototype manufacturing due to the coronavirus outbreak in China. I finally got the prototype circuit boards in today, and it's a go! Pictures:
This is the first prototype assembled. Specs:
* Rockwell R6501Q CPU at 1 MHz (supports R6501AQ at 2 MHz)
* 32KB ROM in 4K segments
* 32KB static RAM
* Onboard serial port
* Two 8-bit parallel ports brought out to headers
* Onboard counter/timer available
* Glitchbus expansion connector
Here's a closeup of the CPU:
The sockets for QUIP-64 packages are difficult to find, and the suppliers that claim to have them want a lot of money for them (the only one that returned my RFQ wanted $18/ea QTY 100). I decided to just use Aries machine pin SIP socket strips. Alignment isn't too difficult, but it's a bit fiddly to get the CPU aligned and inserted. On extraction, the outer pins want to bend, with the 90-degree bends in them becoming two 45-degree bends. One of my R6501Q CPUs had bent pins and, rather than fight it into a socket, I just soldered it to the board.
The SBC is expandable via Glitchbus, the 8-bit bus I designed to be processor-agnostic and first implemented with the 8085 SBC rev 3. When onboard memory and I/O devices are not being accessed, the Glitchbus is active. Since the R6501Q, like the 6502, doesn't have a separate I/O space, I dedicated the 256-byte page at 0xEF00 as the I/O page: accesses to that page pull the BIO**M line high to indicate that an I/O transfer is taking place. Here, the prototype R6501Q SBC is being tested with an 8255 PPI Glitchbus board:
Works fine!
Check this thread for more updates on the development progress. Big thanks to TangentDelta for customizing the eWoz ROM monitor for the R6501Q SBC, it helped a ton in quickly testing the prototype!
Please fill out the survey *especially* if you're going to be at VCF East 2020 and want to build this board!
(knowing you, it's zero)
