daver2
10k Member
Great minds think alike...
I am surprised at this shortfall in the Z80 design.
Dave
I am surprised at this shortfall in the Z80 design.
Dave
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Apple IIe + Softcard : IN and OUT Z80 statements
- Thread starter Wawavoun
- Start date
Wawavoun
Experienced Member
What I have not really understand is why is it a bigger problem for write than for read ?
Because the operation which give problem under CPM is clearly read. May be write dont work but this do not hang CPM.
May be its because the flip flop could be reset by R/W bus signal ?
May be I will start to think to an improved design of the FPU board with in and out latches to avoid timing problems.
But then I will have to read the status byte of the FPU to know if operations are terminated or not...
Because the operation which give problem under CPM is clearly read. May be write dont work but this do not hang CPM.
May be its because the flip flop could be reset by R/W bus signal ?
May be I will start to think to an improved design of the FPU board with in and out latches to avoid timing problems.
But then I will have to read the status byte of the FPU to know if operations are terminated or not...
daver2
10k Member
It is worth looking at this (modern) design: http://www.s100computers.com/My System Pages/Math Board/Math Board.htm.
The /PAUSE signal can be used on the S100 bus - but it seems as though in this design it is polled by the CPU after writing a byte to the COMMAND or DATA port of the AM9511.
Note that in this design, the AM9511 is driven by an 8255 PPI - so the data bus to the AM9511 is effectively latched (if I have read the design correctly to start with). EDIT: Ignore this statement, it is not correct... The AM9511 data bus is driven from the S100 bus via data bus buffers. Are these latched though I wonder? EDIT2: They have inserted the link on their board to enable the S100 RDY signal from the AM9511 /PAUSE signal - so the main CPU driving the AM9511 will be 'paused' whilst an input or output cycle is in operation.
My guess is that your 0x1A command is not being actioned by the AM9511 device and you are reading from the AM9511 data port the default quiescent value.
Dave
The /PAUSE signal can be used on the S100 bus - but it seems as though in this design it is polled by the CPU after writing a byte to the COMMAND or DATA port of the AM9511.
Note that in this design, the AM9511 is driven by an 8255 PPI - so the data bus to the AM9511 is effectively latched (if I have read the design correctly to start with). EDIT: Ignore this statement, it is not correct... The AM9511 data bus is driven from the S100 bus via data bus buffers. Are these latched though I wonder? EDIT2: They have inserted the link on their board to enable the S100 RDY signal from the AM9511 /PAUSE signal - so the main CPU driving the AM9511 will be 'paused' whilst an input or output cycle is in operation.
My guess is that your 0x1A command is not being actioned by the AM9511 device and you are reading from the AM9511 data port the default quiescent value.
Dave
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