Building a 5170 memory card (for all system memory)

[sponaugle]

I have a couple of 5170 systems, and one of them has significant number of bad DRAMs. While you can still get some of stacked DRAMs from ebay, the supply isn't huge, and the cost to replace all 512K is pretty high. Based on a conversation between a few other members a while back:

https://forum.vcfed.org/index.php?threads/ibm-5170-restoration-psu-fixed-now-ram-problems-sram-replacement.79704/

I thought it would be fun to make an ISA 16-bit memory card that could replace all of the system memory, including the onboard DRAM. This will require a small modification to the main board, as well as a 16-bit memory card that can provide the needed memory mappings.
I thought it valuable to start a new thread to encompass the design and build work.

This is a relatively simply ISA card, and I have done some ISA card design back in the 90s as well as a few PCI cards in the 2000s, but it seems most of that has faded from my memory!

The goal is to have a 16bit (only) ISA memory card that has somewhere between 1 and 4 MB of SRAM, and is capable of mapping that SRAM into any part of the system memory. Constraints: SRAM only, no DRAM so no REFRESH. Through hole mount components if possible for easy building. Surface mount version would be doable, but if we can get a though hole first that would be preferred. All components available new from Digikey/Mouser/etc.

I am going to use DipTrace for the schematic design and PCB design, which is a departure from the usual KiCad or other popular tools - Only because I have used it a lot, and it is a very fast to learn environment. As far as parts selection, I want this first version to be very flexible so I'm going to use an ATF1504 CPLD. It is a PLCC-44 part, so through hole socket support, JTAG programming, 7ns, and very flexible. The design langauge (CUPL) is very easy to write and follow (although the actual tool WinCUPL is a masterpiece of frustration!). For the RAM I'll use the AS6C4008s, a 512kx8 through hole SRAM that you can buy new today, 5V, and 55ns so plenty fast enough.

 

[sponaugle]

Initial Schematic:

 

[sponaugle]

First pass at a PCB:

 

[sponaugle]

And the CPLD code:



(Open Collector for those ISA signals. It could also be tri-state, but I think OC will work)



Input pins, from ISA bus, plus a 4 dip switch for config.



Outputs - Back to ISA, plus controls for SRAM and buffers.



Latch for LA address bits. Not entirely needed as you could do it a different way latching the control signals on the MEMR/W, but this is easy/cheap to do.




For testing - I put the MEMORY all above 1MB just to see if things work. Once this works I could do the system board mod and map the memory starting at address 0.

 

[sponaugle]

Controls for the SRAMs - CS is the key for selecting which SRAMs are on.



Control for buffers. Those last two could be one, because you can drive all 16 data lines even if the CPU is only reading one of the two 8 bit paths.

There is a near 100% certainty that there are mistakes here and in the schematic so feel free to ask/point out/correct/etc! I'll make a pass over all of it again and make sure the dots connect.

 

[sponaugle]

Speaking of mistakes!

BANK0_ADDRESS_ACCESS = laaddr_field:['h'01XXXXX];  /* Second Megabyte of System Memory */
BANK1_ADDRESS_ACCESS = laaddr_field:['h'02XXXXX];  /* Third Megabyte of System Memory */
BANKN_ADDRESS_ACCESS = BANK0_ADDRESS_ACCESS # BANK1_ADDRESS_ACCESS;

Those field values (at least the 3rd one) should be X, which means 'don't care', instead of 0. The last 4 could be either since this field is defined over only 7 bits.

 

[alank2]

Looks cool!

 

[pipmastah]

Excellent project! Lovely work

It will be very useful for overclockers as well as the original 128K-bit DRAM chips are only 150ns rated (or even 200ns in some cases) so I think 10 MHz CPU/bus speed will be the max for these chips with 1 wait state. I already socketed and replaced the 6 MHz bus controller and the clock generator with 10 MHz parts. All of the modifications I do are 100% reversible.

My 5170 board type 1 is currently running at 10 MHz and has a 40 MHz 286-to-486 upgrade installed so I can run things like Windows 95 on my old gal which is turning 40 next year. I just wanted to see how far I could take this and how much could get out of the last common IBM ancestor from which all of the clones are derived

This excellent SRAM board is right up my alley as it will take out the weakest link of the equation in my case, which is the 150ns conventional memory which is of course a huge bottleneck on a "486" (-ish) ;-)
The memory I have on my ISA boards is much faster but they're only able to "back fill" to 256K which is my current configuration (I didn't want to fry my precious piggyback chips ;-)).
I disabled bank 1 by changing J18 to the north position so I have around 25 spare 128K-bit chips in case the 18 chips in bank 0 go bad ;-)

 

[maxtherabbit]

There is a fair amount of false information floating around on the net regarding the sampling of MEMCS16#. The 5170 and true clones do NOT sample it twice. It's only sampled at the falling edge of ALE.

Practically what this means is you can only qualify your MEMCS16# assertion on 128kB boundaries, because you only have the LA bus to go on. Unless you think you can meet the timing of decoding the lower address bus and making your assertion within the pulse width of ALE

 

[dabone]

What's the chance of this working in a XT/286 (5162)?