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Cheapo IDE interface for Model 4p running MM CP/M

The latest revision to my breadboard includes passing the /iow and /cs0 thru the 244 line driver to the ide interface connection. Before this only the /ior and /extiosel passed thru the 244. This changed allowed the cf to work reliably but the read countdown clocking for the drq flag stopped working. Sort of odd. By passing the other 2 control lines thru the 244 everything is working fine including the countdown clocking. All media types, 3.5 ide, 2.5 ide and Cf, work flawlessly with the cp/m driver and format program.

I am still looking at the LDOS hd driver to see if I can setup some debugging to figure out what is going wrong there.

Leeb, thanks for the post, I will take a look.

Matt
 
Problem is I last tried Z80 assembler back in the late 70's on my Model 1. So I am very rusty.

Matt, What program are using as the Editor/Assembler on your model IVp? The LDOS version I am guessing.
 
Got it thanks.

Confusion time...Pearce_jj: you are using 10k pull ups on the address and certain control line. I thought they were supposed to be 1K pull ups?
Which is correct?
 
I don't think it really matters too much, my PC/XT designs have always used 10k so I stuck with that :)
 
I spent some time this morning cleaning up the CP/M driver and loader source code. I think this part is pretty much done.

Now working on messing with the LDOS driver and formatter source.

Matt
 
I've also made a few revisions - added a load of missing ground connections, included A3 in address decode, changed the 245 and 688 to be HCT since it seems likely the target will be CompactFlash (in practice any type should work mind), repositioned holes and tidied up generally.

Updated archive here.
 
Ahhhhh I got a LS688. And started to wire up. Now I have to remove ground from pin 3! No big deal there is that the only major change? Also What can I do with pins 1 and 19 I reversed the position of the 245 so I can use "B" side as input?
 
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To use the 245 with the A side connected to the IDE header, you'd need to add an inverter to the direction pin (pin 1), assuming you're following the rest of the circuit? Yes A3 is the only real change other than a bit of grounding, all along even numbered pins of the 50-pin header in particular, and some grounds were missing from the IDE 40-pin header too.
 
Just turned it around power and grounds on the LS245. And the bypass Cap as well. So can use "A" side as input. Nothing else was hooked yet. Yep all even numbered on the TRS-80 side are grounded and then attached to system/Power ground.
 
Status prototype built and seems to be working in as far as the port responding. Port 47H being the most critical and it is returning the value of 80 decimal as it should. Tried running the TRS-IDE driver on it and received the error message "Note: Drive appears to be unformatted." So far this is the most success I have had using that driver. Will try standard TRS-DOS 6 HD driver but not my breath on it working. But who knows.!!

Oh BTW that's using an 80MB WD hard drive and a 2gb CF card.

Tried regular RS driver. Locks up system.

Matt, any luck modifying the driver code?
 
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I have gotten quite a bit farther with the LDOS drivers. I dumped the version in the ide.dsk image and went with the unhacked originals. With very minor changes it can now make it thru the verify step and aborts with all grans locked out. I think there is an issue with writing the directory track.

The heads and cylinder settings work. Formatting appears to work.

I will debug the directory thing tomorrow.

Matt
 
Chromedome45 said:
Status prototype built and seems to be working in as far as the port responding
Click to expand...

Good news! Is this prototype built to the circuit diagram of my proposed PCB? And how is *EXTIOSEL being driven?

Also, how are we connecting this thing; is there some standard cable already?
 
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Matt: keep hacking away if anyone can do it I think you can. I know TRS-DOS formatting of floppy disks places the directory in the middle of the disk.
So keep that in mind.

Did you say the originals were working sort of? You mean the standard TRS-DOS/LDOS or the original unhacked IDE.DSK originals? Slight confusion!

Pearce: Prototyped using your circuit diagram and *EXTIOSEL is being driven by ACT32 straight to pin 8 no pull ups or pull downs.

Cables: 50 pin card edge from TRS-80 to 50 pin IDC to board and standard 40 pin IDE from board to hard drive/CF card.

So right now I think software driver is main issue. Hopefully Matt can get it going.
 
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Frank: is your model 4 a 128k ram version?

I found the original source before it was hacked for "IDE". Much easier to work on the original which really doesn't need that much change. I DO see the format routine writing to the middle of each sector. At the moment its writing the wrong stuff I think. It looks like the format routine builds up this GAT buffer and tries to write that to the directory track. I will look at it today.

Matt
 
Some positive news to report. Matt sent me a CP/M test program that formats and verifies a CF Card and it worked fine. Now have an M: drive and can copy files to the CF card. So Pearce: looks like this is a working design in so far as CP/M goes. Matt is still hacking away at the LDOS drivers.
 
I've finished off the PCB design - a few small changes:

  • Added buffering to the remaining four unbuffered lines via another 74ACT32
  • Replaced 2-pin header for power with screw-terminals

If we're generally happy I'll send the design to fab.
 
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