Chuck(G)
25k Member
That Iol for the 4116 is the "maximum", not the average, so you're still well within the static current margin.
No, what you have to worry about is C(iA), the input capacitance of the address lines. A quick look at the datasheet shows between 4-8 pF for the TI TMS4116. Since you have 8 chips in a row, you're looking at between 32-64 pF, which is a pretty heavy capacitive load for an LS157 at 4MHz! It was the practice back then to insert small resistors in series with the address lines to damp the effects of a capacitive load, but it's still asking a lot.
Back when I was designing with these DRAMs, I'd specify the "S" part. Of course I would not have used the 74xxx part, because by the time 4116s became available it was obsolete technology.
No, what you have to worry about is C(iA), the input capacitance of the address lines. A quick look at the datasheet shows between 4-8 pF for the TI TMS4116. Since you have 8 chips in a row, you're looking at between 32-64 pF, which is a pretty heavy capacitive load for an LS157 at 4MHz! It was the practice back then to insert small resistors in series with the address lines to damp the effects of a capacitive load, but it's still asking a lot.
Back when I was designing with these DRAMs, I'd specify the "S" part. Of course I would not have used the 74xxx part, because by the time 4116s became available it was obsolete technology.