Welcome to Board #4!
[Link to Original Thread / Board #3]
Initially the address on the ISA slot wasn't reading correctly during ground I/O CH RDY procedure (simiar to Board #1) and as in Board #1 the address bus chips (U7 / U9 / U10) were not enabled. I took a look at U98 & U67. As in Board #1, there was a problem on the CLR line to U67, but this time it was an input to U52 at fault (/HRQDMA) rather than U52 itself. That led me to the DMA controller...
I assume the DMA controller failed at some point because it had been socketed (I also noticed the chip was removed from the "donor" board, presumably it was this replacement) and there was a bodge wire to replace a damaged trace. During inspection I found out that the two lowest IC pins (20 & 21) weren't connected due to faults under the socket. I bodge wired them and the board came to life, passes all RDR tests. (I guess the universe tortured us enough with board #1??
)
[Link to Original Thread / Board #3]
Initially the address on the ISA slot wasn't reading correctly during ground I/O CH RDY procedure (simiar to Board #1) and as in Board #1 the address bus chips (U7 / U9 / U10) were not enabled. I took a look at U98 & U67. As in Board #1, there was a problem on the CLR line to U67, but this time it was an input to U52 at fault (/HRQDMA) rather than U52 itself. That led me to the DMA controller...
I assume the DMA controller failed at some point because it had been socketed (I also noticed the chip was removed from the "donor" board, presumably it was this replacement) and there was a bodge wire to replace a damaged trace. During inspection I found out that the two lowest IC pins (20 & 21) weren't connected due to faults under the socket. I bodge wired them and the board came to life, passes all RDR tests. (I guess the universe tortured us enough with board #1??
)