Some small items of progress and some clarification today.
Clarification first. I'm not only building a 680X0-based PC. I'm starting by building a prototype expansion card for the Sinclair QL that offers at least CPU, RAM and flash, and the video subsystem in the first iteration. Once the community writes drivers for that, I will sent the people who contributed a second board that is the same, but also has the SuperIO on it. Once that has drivers, everything exists to run QDOS/SMSQ on the machine without any original QL parts. At THAT stage I'd be working on the ATX board. I think it is important to do it this way for a couple of reasons: firstly, the QL is my home community. I owe them something remarkable. At least Q40i/Q60 grade. And, for getting me here, the QL community deserves a payback that is a little more enthralling than what is currently available. People have the Q68 but still long for the Q40/Q60. Q60 was a wonderful place to be, and I think it is the peak of QL development, easily out-QLing the CST Thors.
Last night I got a Pentium cache RAM working on a 68EC030. 7.5nS SRAM of 128Kx36, so 512K of zero wait state overkill memory. The memory is so quick that I can copy its entire contents to another cache SRAM in between 68K accesses around 140x/second. It could be a wonderful target for some hidden DMA. I could move 4x long words (16 bytes) in half a clock. Amazing. The interest in these synchronous SRAMs is they're so specific and specialist there's simply no market for them. They're available and incredibly cheap.
I acquired a reel of 2500 clock buffers. The buffers are ICS9112BG as I maybe mentioned before. Datasheet here:
https://www.mouser.com/datasheet/2/698/REN_9112_17_DST_20101122-1996920.pdf The fun part of this IC (and of having 2,500 of them) is that it has 9 buffered outputs. I can give each section that needs a clock its own isolated buffered clock. No circuit will degrade the clock of any other section. I have decided to give each expansion port its own channel of isolated clock based on advice and experience of @zigzagjoe and his many wrangles with clock quality issues on Mac SE/30 PDS cards. Keeping clock domains separate is critical to signal hygiene.
I have honed in on a final expansion bus layout that will address most use cases without putting a huge burden on lighter uses. It is effectively a buffered processor bus system, with each slot having both full access to the entire bus for flexibility. Each slot has a pre-decoded select signal that can be used for simplicity, or ignored. Cards can use space not used by neighboring cards.
M.2 SATA will likely appear at some point, I have a verified schematic that's proven working. M.2 SATA small cards are
ridiculously cheap. The interface and new products will likely be around for some more years.
