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Hobby computer

Crypticalcode0 said:
I probably could but the S-100 bus would most likely end up being the bottle neck in my design then....
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Hi

I really don't think so. Maybe if you went all 8 bit and old school S-100 (Altair and IMSAI). However the later S-100/IEEE-696 systems support full 16 bit bidirectional data bus and 24 bit address bus. Processors like 68K, 8086, and 80286 are able to use the bus in a full extended memory 16 bit mode at full clock speed. All the S100computers.com/N8VEM S-100 boards are fully IEEE-696 compliant and are able to reach respectable speeds especially on actively terminated backplanes.

As someone mentioned earlier, we've gotten S-100 (IEEE-696) CPU routinely boards going in excess of 10 MHz. Certainly 12-16 MHz is possible which is the CPU clock speed of most first and second generation 16 bit CPUs.

The N8 (non S-100 Z8S180) goes 18-29 MHz depending on the configuration. It uses weird CPU clocks though since they are also used to provide timing for the ASCI serial ports. It could go up to 33 MHz IIRC assuming a separate ASCI clock source.

I don't think bus won't be the limiting factor. Many other things will limit how fast the system goes like bus logic timing, RAM/ROM speed, IO decoding, etc long before the bus slows things down.

Thanks and have a nice day!

Andrew Lynch
 
Well, do you have two MC68000 chips? Try running them both half a clock apart to implement virtual memory management (Apollo, ISTR did that). Yes, you can use later versions of the chip to accomplish this, but there's something charming about the Apollo solution.
 
Crypticalcode0 said:
I thought the 68882 would be a little hint together with the SIMM72 that i am aiming at a 32 bit system with some 8 bit and 16 bit parts.
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If you have vanilla 68000s, though, you're stuck with a 16-bit bus anyway - the 68k series didn't get fully 32-bit until the 020. If lynchaj is right about the later S-100s, then you'd be just as well-off building it with a 16-bit expansion bus and be able to drop in some other components later if you feel like it.
 
Chuck that trick was used by SUN too wasn't it?

Commodorejohn i am not stuck with Vanilla 68K's, my favorite CPU out that family is the 68030 because it is somewhat bus compatible with the 68K yet has very advanced for it's time features.

But Chuck if memory is fast enough they don't need to run half speed they just need to be 90 degrees out phase with each other.(Old Z80 trick)
Besides that if memory is not fast enough you could Isolate on from the memory bus and let it have it's data a clock cycle later.
 
Yeah, the 030's a good chip. Too bad they never made it with a larger cache...still, compared to the 386 which didn't have any, it's good stuff.
 
Crypticalcode0 said:
Chuck that trick was used by SUN too wasn't it?

But Chuck if memory is fast enough they don't need to run half speed they just need to be 90 degrees out phase with each other.(Old Z80 trick)
Besides that if memory is not fast enough you could Isolate on from the memory bus and let it have it's data a clock cycle later.
Click to expand...

I think so, but I'm not certain. At any rate, I didn't say "half speed", I said "a half clock apart"; i.e. out of phase.
 
Crypticalcode0 said:
I thought the 68882 would be a little hint together with the SIMM72 that i am aiming at a 32 bit system with some 8 bit and 16 bit parts.
Click to expand...

Hi
I can't wait to see what you come up with. Are you planning on making PCBs, wire-wrap, breadboard, or something else?

Thanks and have a nice day!

Andrew Lynch
 
I have access to PCB proto type tools, Andrew TY btw for Gerber files. ;)

@Chuck i made a workaround which should allow a system to multi thread and adds Virtual addresses like a sun system i didn't saw much use for letting two CPU's run exactly the same code.
One problem is that is uses the highest priority interupt.
I am limiting my design for now to use 8 514400 DIP's, making use of a dumb hidden RAS refresh, and CAS has 4 lines using A1 UDS LDS lines.(Dumb as in unaware of latest access)
At boot time ROM overlays the RAM untill a 7474 gets set.

When i am finished with the DMAC I shall publish the schematics.
It will not fit a Euro card, but so far i managed to keep it all on 2 layers which is the limit with my tools to reproduce locally
 
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If you're using 68000 (not 680x0), how do you get virtual memory to work? Not all instructions are restartable in the 68000--this was a very common issue. Apple got around it by simply declaring those instructions out-of-bounds, but I never considered that to be technically very satisfying.
 
Like you said i do a boundary test in the decoder.
I trigger a BERR on the CPU on which it occurred trigger the highest interrupt on the companion CPU and let the one who entered the faulty address enter a Halt state.
When the companion finished the Interrupt loop reset the initial CPU with the correct data

Only trouble is and i am still figuring it out what is the best manner how to prevent a race condition when both run into trouble.
And there are a few things bothering me doing it this way, exception vectors and such.

I better read chapter 6 of the 68K user manual one more time.
 
I found a flaw in my Logic.

When a either a read or write tries to go out of bound and this is a register set value which should be set during boot.
It triggers a double bus error on the CPU going out of bound resulting in a system Halt for that CPU.
The second/companion CPU would receive a interrupt and get a vector this would be somewhere in ROM which should point to a address buffer which holds the other CPU's stack data and use that to do the Virtual operation.(CPU's are cross wired so they refer to each other as the second CPU and assume they them self are the main, be careful!)
at the end of the interrupt the second/companion CPU should set the lowest address to the stack pointer of the other CPU.

The upper most 2MB are cross addressed so the stack pointers grow toward each other!!!
The lowest 8MB should be shared Memory but this does not need to be fully occupied.
There is 2MB address space for ROM, these are not shared by the CPU's and overlay address 0 at cold boot.
And the other 4MB are for Board resources, for now i need some more Ideas.
This would make the memory map something like this.

000000h to 7FFFFFh Shared Memory
800000h to BFFFFFh Board Resources
C00000h to DFFFFFh ROM, this is not shared between CPU's
E00000h to FFFFFFh Mirrored RAM, this is cross wired to let the stack pointers grow toward each other, I assume that 1MB should be a safe margin as long no one pokes around at random in this space.

I use 2MB slabs because I can simply use a 74 138 to decode the space it points to.
At this point I would also like to say Each 2MB Address Slab has it's own 16bit data path.
If i would use 4 68K's i would have gone for something different.
 
Okay I modified my concept I added several features DMA is one of them.
I use a 12 bit counter and a 4 bit counter to get to 16 bits.
Added 4 registers Status, Base address, Repeater/chain, and Block length.(first two registers are mandatory, later 2 are optional)

I am not sure yet if i should enforce variable block length over the repeater or when the repeater value is 0.

I also modified the Memory map so Now i have smaller segments of memory so i can have more parallel work.

Here is the altered memory map, added more memory after doing some more study.
000000 - BFFFFF is Memory in 1MB segments looking at a method to get this down to 512KB.(I was thinking of using these Demux for RAS lines)
C00000 - DFFFFF is Board resources and 512Kb ROM for each CPU.
E00000 - FFFFFF is Stack space, still mirrored.

All registers are now word length and word aligned.
Contemplating splitting address and data bus for each 2MB segment.
 
Hi
Your design is unclear to me. Do you have a block diagram or schematic? I gather it is a 68K series CPU or two and DRAM with maybe some IO. What are the details?

Are you using KiCAD or some other EDA?

Thanks and have a nice day!

Andrew Lynch
 
Still in a pen and paper stage but in general i use ORCAD.

Okay, A quick sum up then.
2 68K's as CPU's.
Fast Page mode DRAM
2 ROM's 27C4000 or smaller i just reserved the 512KB address space for ROM.

Just a question if not accessed should it RAS refresh the Memory segment?
 
I need some Ideas/counter proposals for the Board resources.

I have a lot of space for board resources I intend to add at least a FDC and perhaps even IDE since both require relative little address space.
 
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