Imsai 808 Front Panel Woes

[Endersending]

Hello Everyone!
I am a new member to VCF and a new owner of an IMSAI 8080 Computer.
Here is the specs of the computer
IMSAI (Fulcrum clone I8080)
CPA Front panel (not sure the revision, date code 1981)
ZPU board: link here: http://www.s100computers.com/Hardware Folder/Cromemco/Z80/ZPU.htm
64K Dram memory board: http://www.s100computers.com/Hardware Folder/Measurement Systems/DMB 6400/DMB 6400.htm
The back plane is a 22 slot Wonderbus.
- I have read the manual for the ZPU and memory board, and I think I have to set properly.

I have a million questions about this machine but I will start with my main problem and hopefully can get it fixed first.
My problem is the front panel operation. I have the schematic and I have been doing lots of troubleshooting, but I am getting confused on which pins/bus need to be working for certain operations.
First: When I power on the machine, or do a reset, the PROGRAMMED OUTPUT lights do not light up. not sure if this is a problem, but something I noticed. Watching videos of the IMSAI 8080 everyone else has OUTPUT lights on when the macine first starts. The lights do work; if I set the machine to RUN, you can see them work and when I do a single step they come on at certain times, just not on a RESET or power on.

The main problem is not being about the deposit into memory. I can hit EXAMINE, and the ADDRESS lights show the right address. If I try to deposit, it doesn't seem to accept the value. I can see the DATA BUS lights flicker as I hit depost (if the bit is set to 1) like it tries to send it, but the computer doesn't take the new values and and leaves the original values on the DATA BUS. There are two reason I think this is happening: 1) The memory board is not configured correctly. 2) a bus signal is missing that should be enabling the memory to accept the write request.

The memory board is configured as one bank of 64K. You can set the card to have different banks to select, I chose one large 64K bank. looks like the 16K banks are lined up, and a single user accesses them at each address. starting at 000H,4000H,8000H,C000H. When the machine is on, 4 LEDs on the card light up showing all 4 banks are active.

I read on another thread that maybe I need static ram? maybe someone could explain why static and Dram are different. I understand Dram needs to be refreshed, but not why it can't be addressed directly like static ram (maybe what I read is wrong)

This leaves me with a final question: Do I need a memory board to input instructions to the processor? the ZPU board I have auto loads a jump address on boot (defined by switches on the ZPU board) where is it storing that? on the stack of the CPU?

I have probed different busses while the RUN switch is active. I would power on and hit RUN and then RESET once in awhile just so I could see activity on the BUS:
+8, +16, -16v, Ground are all OK.
pins 3 - 23 Did not show anything
pin 24, 25 clocks are OK (should be 4mhz but only seeing 2mhz signals?)
all Address pins A0-A15 work, 16-23 are dead (no 24 bit addressing being used I assume)
all DI0-07 work
all DO0-07 Work
pin 44 sM1 OK
pin 47 sMEMR OK
pin 49 2mhz clock OK
pin 68 MWRT OK
pin 96 sINTA not working.. I will test this one more
pin 99 POC ok

Using the schematic, I traced the DEPOSIT from U15.S to Bus 21, which seems to be working.
Any help is appreciated. Thanks!

 

[Dwight Elvey]

The light for the output don't have any specific state on reset, that I know of.
Different memory boards do refresh differently. Most for the S100 use independent refresh from the processor. Some boards that know that they have a Z80 processor let the processor generate the refresh. This does take some ROM code, when using the Z80 refresh counter, to turn the Z80 refresh on.
Otherwise, DRAM should look just like static RAM to the front panel. The fact that you see values in the RAM would tend to indicate that the refresh is working. For DRAM, this usually powers up with a consistent pattern and a few bits here and there that are changed, at some locations. Anyway, not totally random.
It sounds like you are not generating the write strobe on the bus. The fact that you see the data flicker would seem to indicate that the data bus is being driven.
I don't know how much you understand about how the front panel board works, so I'll describe a little.
The front panel uses the processor to generate the address, by jamming instructions on to the processor. When you increment the address, the processor does a NOP. When you enter a new address, the processor does a JMP instruction. The front panel puts these instruction onto the processor directly, to the processor, with the cable from the front panel to the processor board. The S100 data bus is isolated from the processor when the front panel in not in the run position. Otherwise, the front panel fully controls the S100 bus while the processor supplies, only, the address. Read and write is controlled by the front panel.
The fact that the data flikers would indicate that the open collector drivers and the state machine is sequencing. You need to scope the write pulse to the bus. Also, the fact that the CPU board a a Z80, would indicate that it is setup for DRAM. The older CPU cards often required modifications for DRAM memory.
You can always look at the memory board by looking at an address line of one of the memory chips. If refresh is working, from the memory board's refresh controller, you should see the address changing. It has to make a pass through 128 addresses in less than 2 milliseconds.
If it doesn't it may be expecting the Z80 processor to be generating refresh. As I recall ( I could be wrong ) but I believe one needs code to enable the Z80's refresh counter. In other words, a boot ROM.
Dwight

 

[Endersending]

Thanks for the reply.
For the D-ram: I think the board creates its own refresh. Also, The board is set for 'address mirroring' Which states it mirrors the Low bytes onto the High bytes of the address line. Not sure if this should be changed. Maybe someone could what address mirroring is good for.

From what I have seen, When I hit DEPOSIT, I see a SLOT 68 (MWRT) pulse. I think the CPU takes that pulse, senses a write, and signals the DRAM on SLOT 77 (pWR). If I hit RUN, I can see data happening on SLOT 77. This does not happen from the DEPOSIT switch. Its like the CPU ignores the SLOT 86 pulse (when in STOP position of course) or the logic isn't getting propagated down stream like it should (bad chips, etc..).
After doing some more research, I decided that it is worth cleaning all the socketed chips on the ZPU. I feel like that might clear up this problem.
The panel seems to 'work' and maybe it's the ZPU board that is not completing the write.
I broke a leg on a 7436 Hex buffer trying to clean pins. I will get that replaced and report back.

 

[Dwight Elvey]

Like I was saying before, all the CPU does is either JMP or NOP. All the other S100 bus operations are controlled by the front panel. The CPU does not have any write operation. Since you can examine ( JMP ) and step ( NOP ), that is all the involvement of the CPU board. If there is an issue, it would be the front panel, the back plane, the DRAM board or the spec between the front panel and DRAM board. Some of the signals have been redefined since the IMSAI was made.
Typical DRAM boards of that time frame that expected to do their own refresh would have a delay line module. It is unlikely to be done with resistors and capacitors.
Dwight

 

[Endersending]

Thank you for the reply.
I have been probing and reading, and even bought a bus probe card but I still don't feel any further. Right now, I feel confident that everything is working, just not talking.
So this would mean the problem is the front panel and the DRAM board communication.
the DRAM manual says it has its own refresh.

From the manual this is what I understand the DRAM board doing:
It uses pSYNC [pin 76] and sM1 or RDEN (which is pDBIN or sMEMR)
I think I use sM1 (which is the first cycle of an execution?)
deposit switch create a pulse on pWRB [pin 77] of the s-100 bus.
This seems simple enough that it needs a rising clock pulse, and if pWRB is low, it's in write mode.
There is a few bus lines are are used, and might not be configured correctly:
sOUT [pin 45] and pWRB = 1 means I/O instruction is executed (not sure if this matters)
theta2 [pin 24] - Clock 2?
theta1 [pin 25] - Clock 1?
sINTA [pin 96] - Wired low via board jumper since from what I see, I do not use this line
pWait [pin 27] - Processor waiting - Wait states? Do I need them?
PHANTOM [pin 67] - pulled up via jumper on board, not used
pRESET [pin 75] - board uses to reset
pRDY [pin 72] - More wait state stuff. I have no idea if I need to worry about it
xRDY [pin 3] - Another wait state line? Do I need?

At this point I assume one of these lines is not pulled high or low. When I put the machine in the RUN position, I can see activity on the DRAM board.
If the machine is in STOP position. does the DRAM still have the pSYNC or clock pulse it needs to deposit? Is the pulse created by a NOP when the deposit button is pressed?

a copy of the DRAM board schematic is here:

http://www.s100computers.com/Hardware%20Manuals/Measurement%20Systems/DMB%206400%20schematic.pdf

It's difficult to tell what I need enabled since the inputs goes directly into a chip.

I will keep researching and testing.
Update:
The control panel pulses pin 68, but the DRAM board looks for pin 77. I tried jumping them, but didn't seem to do anything except make a deposit act like a deposit next. The processor has a direct ciruit that take pin 77 and puts it on pin 68 but not the other way around.. So strange
Why are these on different buses? this is what made me think the CPU has to interact. maybe I can jump the Dram board for pin 68.

 

[Endersending]

Another update:
I found a listing for this DRAM card in an old magazine:

https://vintagecomputer.ca/files/MiniMicroMart/MiniMicroMart-Catalog-Winter1979-80.pdf

page 10 has an advertisement:
Fantastic Buy! ... MEASUREMENT SYSTEMS & CONTROLS, INC. A high-quality, extremely well-designed memory board. Fully compatible (except for front-panel) with all known 8080 and Z-80 systems to 4 MHz, without wait states; fully socketed; assembled, burned-in, and tested.

So, I assume this card was not designed for a front panel which is why the enable pins are not on the same bus.
So this leaves me with 2 options: modify the memory board to work with the front panel, or get a different memory board.

Any suggestions on modifying the board? I would think I would just buffer pin 68 over to pin 77.

 

[hmb]

Another update:
I found a listing for this DRAM card in an old magazine:

https://vintagecomputer.ca/files/MiniMicroMart/MiniMicroMart-Catalog-Winter1979-80.pdf

page 10 has an advertisement:
Fantastic Buy! ... MEASUREMENT SYSTEMS & CONTROLS, INC. A high-quality, extremely well-designed memory board. Fully compatible (except for front-panel) with all known 8080 and Z-80 systems to 4 MHz, without wait states; fully socketed; assembled, burned-in, and tested.

So, I assume this card was not designed for a front panel which is why the enable pins are not on the same bus.
So this leaves me with 2 options: modify the memory board to work with the front panel, or get a different memory board.

Any suggestions on modifying the board? I would think I would just buffer pin 68 over to pin 77.

There are technical reasons why an S100 DRAM board design won't work properly with an Altair or IMSAI front panel. If it had been easily possible to make this DRAM board compatible with a front panel the original designers would likely have done so, hence I doubt you will be able to make a few simple mods that solve these problems.

Unlike the relatively simple interface design required by a static RAM board on the S100 bus, a dynamic RAM board requires a far more complex interface. Most of this complexity is required so the DRAM board knows (a) which bus cycles (and where in those cycles) it can run an internal "hidden" memory refresh cycle that runs synchronously with the normal operation of the bus and (b) if normal bus operation is being held in a "not ready" state, in which case the board needs to initiate its own non-synchronous memory refresh cycle. That is why this DRAM board looks at so many S100 bus signals including the system clock, the bus strobes, and many of the bus status signals (for example it looks directly at the pWR and sOUT signals rather than just the MWRITE signal), and the status of the bus "ready" signal.

My recommendation is that you find yourself a 64K static RAM board, which will save you a lot of grief. Most will work with a front panel, or are very easily modified to work with a front panel.

 

[Endersending]

I bought a 32-K static RAM board off Ebay.
I guess we can close this thread as that there was no problem. Just a board that doesn't work with a front panel.

My next step will be making sure that machine works with the static board once it arrives. I have to fix switches on the front that have broken or loose housings.
After that a ROM Board. I would assume if I 'RUN' the machine and load an OS, I could use software to access the 64-K DRAM board. since it has bank select feature, I can turn half the DRAM board off and use 32-K static + ROM + the rest in DRAM.

Thank you for the help. I Learned a lot trying to figure this out.

 

[Dwight Elvey]

You realize that the DRAM board will lose its memory any time you halt to use the from panel!
You should be able to use it as temporary memory. A common use might be to edit a large file ( I'm assuming you'll use CP/M when you get there ).
Dwight

 

[Hugo Holden]

Maybe your DRAM board simply has a fault, and it could otherwise would be working with your setup.

I have done a lot of work on similar DRAM boards, such as the Processor Technology 16kRA card. The delay likes in these are notoriously unreliable. They fail and it disables the card. Other failures are in the old CTS DIP switches that encode the address. And also bad IC sockets/connections. Any of this sort of thing gives a non-responsive card.

It would be worth checking with the scope if there are logic level signals coming out of the delay line outputs. When they fail they disappear out of one or more outputs.

I wrote an article about the ones in PT's card, which explained why they failed and how to replace them with modern delay devices, or, astonishingly, new ones made now by the same company, Data Delay Devices Inc, in Clifton NJ:

https://www.worldphaco.com/uploads/PROCESSOR_TECHNOLOGY_16kRA_RAM_CARD.pdf

 

[Endersending]

I will scope the card and report what I find. The DRAM board has 2 TTLDM-200 chips. Although I'm not sure how the card will work when it physically can't see the MEMWRT pin witht he front panel, where software can run the instructions to access the memory.
As to the comment about DRAM loosing memory on power off or reset: I know this. My first step is to get the computer working with the front panel. And then I will work on a ROM and storage.
This Fulcrum I8080 (IMSAI) will be a many year project. The end goal is to have ROM, floppies, serial, and maybe video and keyboard. and then be able to play Global Thermonuclear War on it (and maybe some chess).
Thank you for all of the help.

 

[Endersending]

Update for the Fulcrum I8080: I received 32K SRAM card today, put it in the machine and it works great.
I have not had a chance to probe around on the DRAM board that wasn't working with the front panel but I have a suspicion it works fine and I will confirm that once I can load some programming onto it.
Right now I am going to program it from the switches, play some games and some day I will get a ROM and serial card for it.
Thank you everyone for the help.
Once I get the switches that are bad replaced, and the unit back together I will post some pictures of it.

 

[Dwight Elvey]

If someone was clever, they could have made an isolation card that would go between the front panel card/cpu card and the rest of the bus. This way it could allow the DRAM card to run when using the front panel card. The idea would be to isolate the main data bus by cutting leads on the back plane board and using an additional slot. Most of the time, the front panel is waiting for a human to fiddle with the switches and only need to isolate the bus for a few micro seconds when doing updates front panel write updates. One could latch the data bus for the display of the selected address.
Dwight