Introducing the Micro-PET

[fachat]

Just in case you haven't seen it, I designed and built the Micro-PET, a Commodore PET re-incarnation: https://github.com/fachat/MicroPET

• Commodore 2001 / 3032 / 4032 / 8032 / 8296 with options menu to select at boot
  • Boot-menu to select different PET versions to run (BASIC1, 2, and 4)
  • 40 col character display
  • 80 col character display
  • 8296 memory map emulation
  • IEEE488 interface (card edge)
  • Tape connector (card edge)
  • PET graphics keyboard, or alternatively a C64 keyboard (BASIC 4 only)
• Improved system design:
  • 1M total RAM: 512k fast RAM, 512k video RAM, all accessible using banks on the W65816 CPU
  • boot from an SPI Flash ROM
  • up to 12.5 MHz mode (via configuration register)
  • VGA b/w video output (640x480@60Hz mode)
  • Write protection for the PET ROMs once copied to RAM
  • lower 32k RAM mappable from all of the 512k fast RAM
• Improved Video output:
  • Hires graphics mode (using a configuration register)
  • modifyable character set
  • 40/80 column display switchable
  • 25/50 rows display switch
  • multiple video pages mappable to $8000 video mem address

See more on its intro video: https://youtu.be/COlfqcaY7rI (or the whole playlist with more build-time videos: https://youtube.com/playlist?list=PLi1dzy7kw1iybjcUccgjCV4fhNH4IPWSx )

Have fun!
André

 

[Ruud]

Great!

 

[whartung]

This is a fabulous job. I really like the way this is done.

How fast is the SPI bus? How is it presented to the CPU via the CPLD? Is it detached and looks like a parallel port to the CPU or is the CPU connected to it directly and the SPI "bit banged"?

 

[fachat]

The SPI should be 6MHz. It's presented to the CPU as three registers. A control register (read status, write CPHA/CPOL, select), a data register (write & send, read & trigger next read), and a peek register (read data register but without triggering another transfer).

The auto-trigger allows fast transfers, just BIT/Bxx loop until ready, then write (or read), except when doing a PEEK. Works as read/writes are qualified with VPA/VDA, so no spurious reads.

https://github.com/fachat/MicroPET/blob/main/CPLD/SPI.md (select is wrong, is now a number in the lower 3 bits, 0=off, 1= Flash, 2= ...)

André

 

[whartung]

The SPI should be 6MHz. It's presented to the CPU as three registers. A control register (read status, write CPHA/CPOL, select), a data register (write & send, read & trigger next read), and a peek register (read data register but without triggering another transfer).

That's pretty good. I'm not logic savvy, so I couldn't do something like this myself. I find bit banging SPI on the vintage CPUs just kills the I/O rate, so I'm always on the lookout for a SPI driver chip that can run the Serial side at "full speed" and look like a UART to the CPU with 8 bits of data and some control lines.

Especially with interfacing to modern peripherals that can deliver far, far faster than vintage CPUs can consume, especially at 8 or 14Mhz, but I think even at 20-30MHz like the modern Z80s can reach.

The idea of reading an SD Card or USB device over a bit banged SPI on a 2Mhz CPU is just...soul crushing.

And that's what I like specifically about this device, is that it does have USB and SD and even Ethernet on board. I'm not even that interested in the PET part, but just as a generic, modern '816, plus the graphics!

I think having a UART like device that can connect to USB for a vintage CPU, and run at "CPU parallel Bus speed" for data transfers would be a great wide open door to a whole new world.

I didn't follow the memory layout much, as to how much of the extra '816 banks are available to everything, but that could all be mitigated in ROM, likely.

How hard would it be to boost the "fast RAM" up?

 

[fachat]

That's pretty good. I'm not logic savvy, so I couldn't do something like this myself. I find bit banging SPI on the vintage CPUs just kills the I/O rate, so I'm always on the lookout for a SPI driver chip that can run the Serial side at "full speed" and look like a UART to the CPU with 8 bits of data and some control lines.

Especially with interfacing to modern peripherals that can deliver far, far faster than vintage CPUs can consume, especially at 8 or 14Mhz, but I think even at 20-30MHz like the modern Z80s can reach.

The idea of reading an SD Card or USB device over a bit banged SPI on a 2Mhz CPU is just...soul crushing.

Exactly my thoughts!

And that's what I like specifically about this device, is that it does have USB and SD and even Ethernet on board. I'm not even that interested in the PET part, but just as a generic, modern '816, plus the graphics!

I am actually working on a more generic board for my CS/A computer, with color VGA output, no PET I/O but a CS/A bus connector to use all the I/O boards from there. http://www.6502.org/users/andre/csa/index.html

I think having a UART like device that can connect to USB for a vintage CPU, and run at "CPU parallel Bus speed" for data transfers would be a great wide open door to a whole new world.

I didn't follow the memory layout much, as to how much of the extra '816 banks are available to everything, but that could all be mitigated in ROM, likely.

How hard would it be to boost the "fast RAM" up?

The issue here is that the CPLD is basically full. Almost all the resources are in use. It _may_ be possible to increase fast RAM output - one more address line from the bank address, a separate select line. If you remove some of the more complex PET mappings (e.g. 8296 memory map) even more could be possible.

André

 

[fachat]

Oh, and btw, there is no ROM. The system boots by copying over some code from SPI Flash to RAM at $ffxx before releasing the CPU's /RES line. But I get what you mean

 

[whartung]

I am actually working on a more generic board for my CS/A computer, with color VGA output, no PET I/O but a CS/A bus connector to use all the I/O boards from there. http://www.6502.org/users/andre/csa/index.html

Sounds nice.

The issue here is that the CPLD is basically full. Almost all the resources are in use. It _may_ be possible to increase fast RAM output - one more address line from the bank address, a separate select line. If you remove some of the more complex PET mappings (e.g. 8296 memory map) even more could be possible.

Understood.

The 65SPI chip is pretty much exactly what I was thinking.

But my thought experiment (never tried) was to interface to a Rasperry Pi 0 (or regular one), and utilize it as the "gateway to the world" via a simple parallel protocol.

The Pi would be running gateway software to manifest the parallel protocol to the host, and "publish" devices, notably the filesystem, USB, TCP/IP, video perhaps.

I figure for a $5 chip, even if imperfect, if the parallel protocol can be clock driven, but not necessary regular, it would be quite a boon for vintage processors.

I think the Pi should be more than fast enough to keep up with most vintage CPUs. I think it's reasonable to have it drive host based ISRs.

Worst part would be the startup time of the Pi having to boot, and that's it's, perhaps, "impure" as its a hardware and software solution.


Your work looks nice, thanks for sharing!