I need to provide an inverted clock signal to my Versafloppy II board, so I wired together a simple circuit on a prototype board: pin 24 of the S-100 bus (master clock) goes into both inputs of an 74LS38N NAND inverter (pins 1 and 2), and the output (pin 3) goes to bus pin 27. The inverter is powered with a +5VDC regulator and has a 0.1uF tantalum cap across its pins.
The datasheet also lists the maximum time for a transition as 22 ns. If two such transitions are required per clock period, doesn't that mean that it should be able to invert the signal from up to a 23 MHz clock? I'm at just 4 MHz.
However this circuit doesn't seem to output anything more than typical noise at a 240mV DC potential. Anyone know what's wrong with using this chip for inverting a clock? How should it be done?
The datasheet also lists the maximum time for a transition as 22 ns. If two such transitions are required per clock period, doesn't that mean that it should be able to invert the signal from up to a 23 MHz clock? I'm at just 4 MHz.
However this circuit doesn't seem to output anything more than typical noise at a 240mV DC potential. Anyone know what's wrong with using this chip for inverting a clock? How should it be done?