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ISA 8 Bit 8MB Extended Memory Card

Thanks, Plasma--that's what I was talking about. Regardless of mapping functions, there are times (quite often) when you need to move from EMS to conventional memory and vice-versa.

Comparing this to XMS isn't qute the same thing--we're talking about an 8-bit LIM card here. You'd need your head examined if you opted for an 8-bit ISA card on a 286 or better system. I suspect this 8-bit card is intended for 808x systems.
 
Thanks, level shifting isn't the problem, rather the packages. I've gone with SOIC as these are pretty easy to handle - quicker that DIP, once you've done a few :)

The layout is nearly finished. I'll post an image in the next day or too.

4x 16KB registers can be used by the ISR as 1x 64KB if desired ;-)
 
PCB layout is done. To recap, this board uses up to 4 of 512KB SRAM chips to provide up to 2MB of EMS. It has four page registers providing four 16KB windows within a 64KB page frame.

xt-ems-r1-pcb-001.png
 
Something like this would slow down my model 25 though, wouldn't it? Since my model 25 addresses it's conventional RAM as 16-bit, not 8-bit.
 
8-bit cards always run at ~5MHz too, unless they assert B8 and the machine supports ZWS. This board is designed for XT class hardware.
 
pearce_jj said:
PCB layout is done. To recap, this board uses up to 4 of 512KB SRAM chips to provide up to 2MB of EMS. It has four page registers providing four 16KB windows within a 64KB page frame.
Click to expand...

While I'm happy to see this, is there any chance it can be designed with something larger, like 8MB or the full 32MB? 2MB is only useful for applications; with 16 or more, a large disk cache could make a real dent in hard disk access times.
 
I went with the biggest RAM chips in SOIC I could find that were sensible money (about £2 each). SRAM helps keep things simple, too as obviously no need to worry about refresh. I guess you're thinking about old MFM drives - with CompactFlash, very much the limiting factor is the REP MOVSW throughput of the 8088 anyway.

So really the answer is maybe, if someone can find some bigger SRAMs :)

To add - retrieving data from CompactFlash with my V3 adapter via DMA, on an 8088, will be *faster* than retrieving from EMS via REP MOVSW, and we save the cache lookup. I've been pondering on the idea of implementing the same logic - and hence CPLD implementation - for an EMS board, but I wonder whether many (any?) apps use function 24h and how much difference it would make (locality of reference and all that). Plus that also ties us to a very non-existent supply of 5V CPLDs.

There are some 8Mb SRAMs available, but they all seem to be TSOP packages, which are very small and likely to put off many assemblers (even the SOIC stuff I think is pushing things).
 
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Just a thought - the design is actually 4MB already, but there's only space for 4x 512KB SRAMs on the board. The 100x100 size limit is imposed by the free Eagle software, and also provides very significant cost advantage for manufacturing.

But, I could split the board into two parts: the address decode and latches, and the a daughter board for the SRAMs. This will enable the full 4MB, but obviously then requires assemblers to make two PCBs even if they only wanted 512KB EMS. Going beyond 4MB means moving to 16-bit latches which makes everything much more complicated, unless we go the CPLD route (or some uController).
 
If it significantly increases the complexity or cost of the board, by all means, feel free to ignore me :) I just threw it out there in case it was easy to do. I have since been corrected.
 
I've kicked around a larger design. I just don't have anytime to work on vintage projects atm - sorry. My day job keeps me pretty busy - which is now turning into a night job and weekend job it seems as well.

https://upverter.com/eeguru/1461fe95496bdc02/ISA-RAMROM-Expansion-Board/

I've used the same memory routing and footprint before with a modified Lattice SDRAM controller design. It works up to about 60 MHz but performs a full burst transfer for every WB access - no caching. All the ISA lines for both 8 and 16 bit operation are present so even though it's a 16-bit card, it could would work in an 8-bit slot assuming there's clearance for the overhang. The intent would be to configure the 8/16 bit mode flag, conventional fill areas, XMS starting (fill) address, and EMS window size and location through an IO port discovered through PnP. The dip switch would to just active the PnP config mode only incase the configured settings were not compatible with the machine it was in. There also plenty of capacity in the PLD for a small MCU to perform shadow loads of option ROMs into mapped RAM on boot and to facilitate fast page to page copies per the LIM spec. 64MB RAM and 64MB flash offer some interesting possibilities like a flash backed RAM disk auto-loaded on start-up. There wasn't enough pins for DMA signals so fast transfers to the host would need to be memory window mapped and rep movsw'd. I had planned to hold the first ISA bus access hostage with a arbitrarily long wait cycle until the startup load from flash was complete - so there would be plenty of time for option ROM loading. The PLD is loaded from internal flash but it also supports keeping a golden image on the external flash for guarantee'd fail-safe updates.

I suppose an 8-bit version could be made with maybe an RTC to go with it. However everyone I've talked to about it always points out the limited demand for ISA memory cards. So I'm surprised to see this thread. The design is on upverter so anyone can run with it. I might get back to it during Christmas time frame assuming work settles down like I expect.

I would recommend changing the design proposed above to through hole if you are just using SRAMs. Would make it hobby friendly.
 
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0.8mm pitch I think many will find daunting. But, by moving to a daughter-board arrangement, that option would be easy to provide.

That said, Alan's board is so very far ahead, seems things have moved on :)
 
No, I have no time to work on it. Any solution that can be here soon is better than mine. At some point, I'll get to it. When and if I do, great. But your hard work is still the most valuable to everyone else.
 
Well, this is the idea. The ISA board itself has the address decode logic and the four window registers, but no memory of any kind. Instead, a 40-pin header:

4MB-EMS-Board.png


Then, a memory module can be connected to that header - meaning that each time the SRAMs go end of life, we only need spin up a new memory module. The ISA slot board itself is just plain old 7400 series ICs so should be pretty easy to source (SOIC) components for. For now, I've laid out a board that can be populated with 1-8 512KB modules, so providing up to 4MB:

4MB-EMS-RAM-Module.png


The driver (/BIOS) will be able to determine the memory installed by simply testing a write-then-read from the first byte of each 512KB physical region within the EMS memory space, the pull-up network ensuring FFh will be returned if no memory chip is present.

These PCB layouts are essentially complete so just need a bit of peer review, and to confirm Seeed can actually do 0.3mm vias, and we'd be good-to-go.
 
I guess the enthusiasm for this board has fizzled out, with the capacity limitations inherent in my design. But for the sake of clarity, is anyone actually working on EMS driver code for it?
 
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