Looking for Parallel Port Schematic

[MattCarp]

Doe anyone have a schematic of a parallel port (ideally an SPP or EPP)?

Ideally a block diagram or design documentation. I'm interested to know how it works.

 

[MattCarp]

duh - IBM PC Technical Reference!

 

[modem7]

Also, sheet #3 of the schematics at the rear of the MF-100 User's Manual (available at [here]).

 

[bladamson]

I assume the EPP parallel port was implemented with an 8255? Here's about the clearest 8255 schematic I've come across (scroll down to the "8255 only" drawing and ignore the little thing on the left of the schematic): http://www.smbaker.com/diy-isa-game-control-adapter-with-parallel-io

Funny you'd ask this. I just popped into ask about how to go about implementing a 16-bit bidirectional IO port for AT and later class machines, but I'll start another thread for that.

 

[Chuck(G)]

Forget the 8255 - it never was used on the PC as a printer port.

See page D-34 in the PC techref

Note that it's all done with bog-standard TTL. Note one other thing--only 5 of the 6 outputs of the LS174 latch are used, even though all 6 inputs are hooked up. Further, note that the LS374 (used to drive the data lines) has OE/ grounded. Give you any ideas? It did for me, back in 1984. Lift OE/ on the 374 and connect it to 6Q (not shown) on the 174. Presto - you have a bidrectional printer port that conforms exactly to PS/2 convention--that is, bit 5 in the control port switches between unidirectional and bidirectional mode.

The same can be done on the MDA printer port. I was using a printer port for driving IEEE-488 (HPIB/GPIB) devices--even had a mention or two in Nuts'n'Volts.

 

[MattCarp]

I ran across a couple things in the schematic that are curious to me. Maybe someone here knows what's happening.

1) In the schematic, the port address decoder is not connected to ISA bus address line A2. This suggests the first parallel port is available at 0x378 (and 0x379, 0x37A) but doesn't that also mean the port is mirrored at 0x37C (and 0x37D, 0x37E)?

2) I noticed on the Init line to the printer, coming out of the 74LS174 flip flop is a cascade if two inverters. Why invert then invert? The only reason I can think of is to add a tiny timing delay to the Init signal. Is that the case?