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pc xt dma refreshes and card adapters

woreno

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Sep 16, 2019
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hi everybody, i was wondering if anyone knows about (or any online doc) how cards in PC XT that uses dma normally behave, since dma requests for memory refresh are periodic. should the card shorten transfers or so, or have a means of pooling the DMA line for refresh, sync, etc to avoid conflicts? thanks
 

Hak Foo

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I think DMA channel 0 is used for refresh, and other channels are devoted to other devices. I think DMA2 is the one that actually gets used typically, for the floppy controller.
 

modem7

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since dma requests for memory refresh are periodic. should the card shorten transfers or so, or have a means of pooling the DMA line for refresh, sync, etc to avoid conflicts?
Requests coming into the DMA controller are just that, requests, they are not actioned immediately. Certain conditions need to be met. For example, if a request for DMA channel 2 arrives when a DMA channel 0 (RAM refresh) cycle is active, the channel 2 request will not be serviced until channel 0 cycle is finished.

As an example, read the '24.3.1. A Sample DMA transfer' section of [here].
 

woreno

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but what if dma already started and the controller is in the middle of a long block transfer, say to an aligned block of 64K ?
the XT memory refresh ocorrs at every 72 clocks (15.12us) (clock=CLK88) between those 72 clocks, then one should transfer a much lesser amount of bytes within this period
i never though about it, but after reading "https://www.lo-tech.co.uk/xt-cfv3-dma-transfer-mode/"

"DMA on the PC and PC/XT brings with it some challenges:
Programming the DMA controller absorbs many cycles
Control must be returned to the CPU every 15 µs (72 cycles) for RAM refresh"

that's why i'm asking. i think for the original fdc, the dma controller was not programmed block mode (byte mode instead),
but for better controllers block transfers and that logic should be used apparently
 
Last edited:

modem7

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that's why i'm asking. i think for the original fdc, the dma controller was not programmed block mode (byte mode instead),
but for better controllers block transfers and that logic should be used apparently
Okay. Now I see where you are coming from - block mode.

(Note too that the BIOS ROM in the IBM Fixed Disk Adapter also uses single mode [byte mode].)

Control must be returned to the CPU every 15 µs (72 cycles) for RAM refresh"
Based on the fact that the data sheets for the RAM chips used in the IBM 5150 and 5160 specify that refresh occurs "at least one row every 15.6 µs".
 

woreno

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what i was asking actually is how block mode should be handled by cards that uses, block mode in a PC XT. yes, fdc uses single transfer mode.
hence asking if (a possibility) pooling lines and sync etc, so theres a correct release of the dma to allow the next dma refresh.
i have just 2 books (Peter Hans and Lewis Eggebrecth) and none of them goes on this topic, neither i find some online documentation for those cases...
 

modem7

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It's not in my experience/knowledge.

But I can say that in practice, strictly meeting the 15 us requirement may not be an issue. For example, about half an hour ago, I brought out an IBM 5150 motherboard. No expansion cards apart from a video card, thus, it would always boot into Cassette BASIC. In BASIC, I then performed the following procedure MANY times, using different test periods in step 4.

Step 1: Write the byte of 66h into address 40h. [DEF SEG=&H40 followed by POKE 0,66]
Step 2: Read back the contents of address 40h to verify that the write took. [PRINT PEEK(0)]
Step 3: Disable DMA based RAM refresh, which for the IBM 5150 (not the 5160), I did by grounding pin 13 of the motherboard's 8253 chip.
Step 4: Wait for the test period to pass, doing nothing in that time.
Step 5: Enable DMA based RAM refresh (by undoing step 3).
Step 6: Read back the contents of address 40h to see if still holds 66h.

( In step 4, do nothing. For example, a read of address 40h in that period would compromise the test, because a read of address 40h would 'manually' refresh the RAM rows associated with address 40h. )

Every time that I used a test period of 5 seconds, I then, at step 6, successfully read back 66h.
Almost every time that I used a test period of 15 seconds, step 6 resulted in the screen clearing then PARITY CHECK 1 appearing.

So, the TMS4164-20 RAM chips used in bank 0 of my 5150 motherboard, can, without refresh, reliably (within the context of the experiment) hold their contents for 5 seconds. The TMS4164-20 datasheet [here] indicates that all 256 rows be refreshed within 4 ms (i.e. an inter-row period of about 15 us). This is like a factor of a thousand, 4 ms versus 5 seconds.

I have seen similar performance from other dynamic RAM chips of the period.

All of the data sheets show the same refresh requirement. It's as if JEDEC, years prior, to create standardisation/competition, defined a 'baseline' refresh requirement which all manufacturers of dynamic RAM of the era had to put into their data sheets, even though in practice, many chips very greatly exceed the spec.

But maybe there are some make-model of dynamic RAM chips used in the IBM 5150 (and clones) that have a refresh requirement that is close to what is in the data sheet.
 

woreno

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strange, those are basic functions, so it will take always some memory for the code, stack, etc...
also if one ground the reset pin of dma controller, one may have to reprogram again the controller for that channel (as the rom do at startup)
anyway my question was about how cards on xt may use dma block transfer... it would take some logic at the controller to ensure the requirements (?) how the correct way to do it...
 

modem7

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also if one ground the reset pin of dma controller, one may have to reprogram again the controller for that channel (as the rom do at startup)
My step 3 does not ground the reset pin of the DMA controller.

anyway my question was about how cards on xt may use dma block transfer... it would take some logic at the controller to ensure the requirements (?) how the correct way to do it...
Yes, you are still waiting for someone to answer your specific question.
 
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