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Have you got a clock on H8 pins 9 and 12? This device should be a 74LS107 JK flip flop.

Have you had a look at the schematic diagram for the circuitry that drives the VERT DRIVE signal?

Dave
 
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daver2 said:
Have you git a clock on H8 pins 9 and 12? This device should be a 74LS107 JK flip flop.

Have you had a look at the schematic diagram for the circuitry that drives the VERT DRIVE signal?

Dave
Click to expand...
Hi Dave, i'm trying to look at the schematics in fact...i hope this fix helps me learn a little more about the oscilloscope.
 
Ok, so that is quite simple isn't it?

You follow the signal named NEXT back to its source on schematic 7 and that leads us to G8 pins 8, 9, 10, 11, 12 and 13 doesn't it?

What are on those pins I ask myself...

Dave
 
daver2 said:
Ok, so that is quite simple isn't it?

You follow the signal named NEXT back to its source on schematic 7 and that leads us to G8 pins 8, 9, 10, 11, 12 and 13 doesn't it?

What are on those pins I ask myself...

Dave
Click to expand...
I see waveform signal only on pins 11 and 13 of G8!
 
Desperado said:
I have not Sync signal on CPU pin 7 also...
Click to expand...
I don't care at this point in time. That is a problem for later. The VDU circuitry is completely separate to the CPU and runs autonomously. We need to get the VDU circuitry running FIRST.

I will have a look at this presently.

Dave
 
Yes, G8 pin 11 is the clock input.

However, G8 pin 13 is also connected to a clock (B02H) and is used to clear the flipflop when the clock goes LOW (hence the little circle on pin 13 of G8 indicating that this input is ACTIVE LOW).

However, you haven't done what I asked you to do have you? I wasn't only just looking for clocks - I was also interested in what the logic LEVELS were also... Please report these.

However, since you are going to remeasure these signals for me - I would also state that G8 pin 12 (the D input) should also be toggling. So, can you also measure the gate that G8/12 is connected to also (that is G1 pins 1, 2 and 3). Tell me if the pins are HIGH, LOW, PULSING or INVALID.

All we are going to do is work our way backwards...

Dave
 
So pin 2 is the problem.

That moves us back to H5 pins 8, 9 and 10. I hope you are following on the schematic diagram?

Dave
 
daver2 said:
So pin 2 is the problem.

That moves us back to H5 pins 8, 9 and 10. I hope you are following on the schematic diagram?

Dave
Click to expand...
Yes Dave im following this schematic:
 

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Right, so where we are heading is the horrible state machine. This is horrible because, unlike simple logic where the output of a gate is a function of the inputs, a state machine has the outputs fed back to the inputs. As a result, any internal failure is likely to be terminal in that the entire state machine 'jams' and refuses to work.

What I therefore propose is that you check (and report) the state of all of the pins for the following devices:

H5, I1, G2, G3, F2 and F4.

This is a reasonable list, so please make sure you work sensibly and get the correct state of each device and pin. Hopefully, this will allow is to at least analyse 80% to 90% of the state machine logic in a single go...

Your mission, should you choose to accept it... This post will self destruct within 10 seconds!

Dave
 
H5:
1 P
2 L
3 H
4 H
5 L
6 H
7 L
8 L
9 H
10 H
11 L
12 H
13 H
14 H
 
I1:
1 INACTIVE
2 L
3 L
4 INACTIVE
5 L
6 H
7 L
8 L
9 H
10 L
11 H
12 INACT
13 L
14 H
 
G2:
1 L
2 H
3 INACTIVE
4 L
5 H
6 H
7 L
8 H
9 L
10 L
11 INACT
12 L
13 L
14 H
 
G3:
1 L
2 L
3 L
4 L
5 L
6 L
7 L
8 L
9 L
10 L
11 L
12 L
13 P
14 P
15 L
16 L
17 P
18 P
19 L
20 H
 
F2:
1 P
2 L
3 L
4 L
5 L
6 L
7 L
8 P
9 L
10 L
11 L
12 L
13 H
14 H
 
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