I'm working in quartus at the moment. What I am trying to do is to find the translated logic for certain parts of the system control circuits post compilation.
After finding a certain element I am trying to apply an appropriate delay to the output signal of that element which corresponds to the circuit's TTL ICs.
For example in case of the PAL U87 I am trying to create a delay of 15ns which is the specification for the PAL.
For fast TTL chips I add a delay of 10ns each.
So I am working my way through the "technology map viewer" schematic trying to list the circuits and corresponding delays added.
Later I will elaborate this list with the circuits it refers to, so I can later recheck the datasheets and adjust the timings more accurately.
I don't know whether this is actually being compiled successfully into the CPLD by quartus, but I will make a good attempt.
An example of what the timing constraints I am making look like:
Code:
#**************************************************************
# Set Minimum Delay
#**************************************************************
set_min_delay -from [get_cells {inst35~14sexp1 inst35~14sexp2 inst35~14sexp3 inst35~14sexp4}] -to [get_cells {inst41}] 15.000
set_min_delay -from [get_cells {inst25~7}] -to [get_cells {inst73}] 15.000
set_min_delay -from [get_cells {inst41}] -to [get_cells {inst89}] 15.000
set_min_delay -from [get_cells {inst73}] -to [get_cells {inst62}] 10.000
set_min_delay -from [get_cells {inst52~17}] -to [get_cells {GATE_245}] 15.000
set_min_delay -from [get_cells {inst82~1}] -to [get_cells {CNTL_OFF_n}] 15.000
set_min_delay -from [get_cells {inst75~0bal}] -to [get_cells {inst73}] 15.000
set_min_delay -from [get_cells {inst29~7}] -to [get_cells {DIR_245}] 15.000
set_min_delay -from [get_cells {inst96}] -to [get_cells {inst35~8bal}] 10.000
set_min_delay -from [get_cells {inst43}] -to [get_cells {inst77~4}] 20.000
set_min_delay -from [get_cells {inst77~4}] -to [get_cells {SDL_GATE_n}] 20.000
As you can see here, I am applying a "minimal delay" value to the circuits.
the "inst77~4" type of design elements are typical of post compilation representations of the logic in the technology map.
I think the delays are added by the compiler between the design elements of the technology map viewer items in quartus.
After saving the SDC file under the project name, it is automatically taken in by the compiler and applied into the POF file for programming the CPLD at the next compilation cycle.
I tried to generate some VHDL code however it's kind of difficult because the generating program keeps complaining about incompatible names.
So I already renamed a lot of signals however there is still some incompatibility so I left it for now.
I may be totally mistaken but I believe I am seeing some slight improvement after applying some delays.
For example I was able to power up the system within 20 power cycles, and once even after only 6 power cycles.
Which is a lot better than I have seen a few days ago.
It may be coincidental but I will try to apply the correct or reasonably correct delays to all the circuits in the CPLD to match the TTL ICs in certain circuits.
The problem in this process is that sometimes the original circuit is completely gone due to translation by the compiler.
So then I need to trace the circuit somehow to find the technology map area to apply the delay to.
After I make the entire map and list and document every element where it applies to in the system controller, I hope this can provide some kind of improvement, which will tell me if this may lead to some kind of solution.
I also have several steps of verification in mind, and some other ideas to stage-verify the whole design, however those are all more involved "plan B" type of things in case quartus cannot provide sufficient adjustments.
I could design a PCB which resembles more closely the 5170 circuits just as a method of verification.
Then plug it into the CPLD socket and test with that.
Doing this work is not a total loss of time because it can confirm other design areas and eliminate causes.
I think doing this type of verification would be more wise than taking apart the 5170 and working from there.
After all, I know the TTL equivalents of what I am making inside the CPLD.
So going from the theory that timing is the reason for the problems, this could be verified in such a way with a more simple plug in replacement PCB.
I think a double sided design will be more than sufficient to create the system controller contents in TTL.
I would use the U87 PAL design on the board to save some space since that is a match timing-wise anyway.
I proceeded of course straight to the CPLD version of the project in order to be able to test the design.
That I might need further verification work in whatever shape or form, and that I might need further revisions to get to a final design was always in my mind, but I was still hopeful to at least get a system up and running as a development step, which thankfully succeeded. It's not perfect yet, however it is running, and stable as well.
I can apply as many resets and leave the system running for as long as I like, and when I test it, it's still alive, responsive and not crashed.
If anyone has any ideas that may help regarding working with timequest within quartus and applying it to the technology map, I would welcome any useful tips!
Otherwise I will explore quartus further and if I find anything useful for other people who want to work with it, I will share it here.
I may also go looking for some CPLD/FPGA design forums and see if I can find an interested experienced person there who is willing to join in with some useful pointers.
I don't mind inventing wheels, however those do take a lot of time. It's just like reversing the PAL U87, these things are all totally new to me.