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RK05 disk drive versions

I have built my RK05 test interface and currently writing software for it.
Until so far it is doing what I want...

View attachment 1039584
Is this RK05 test interface operating, or is there documentation in a form where it could be cloned? Does it read and write or is the purpose primarily intended to duplicate functionality of the original RK05 exerciser?

To rigorously test the RK05 emulator I was planning to flip the emulator signals so the emulator could be a tester. I think @PDP11GY has done this too.

Considering the following functionality but maybe it already exists?

Select drive always
Unselect drive
Seek to cylinder
Seek loop list of cylinders
Read sector
Loop read sector
Write sector
Loop write sector
Read track
Loop read track
Set mode: RK8E, RK11D or E
Display the mode & status
Display the sector read data
Copy disk to microSD
 
Do the DEC controllers rewrite the sector header when they write a sector?
I stumbled upon my copy of the documentation for an S100 cartridge disk controller a couple of days ago
and the way they deal with sectors is really simple, they do a seek to a track, read a full sector based on the sector
count from index, then to write since they know they are on the correct track, just write out the whole sector with
new sync bytes and header. That guarantees there is no write splice after the sector header
 
Do the DEC controllers rewrite the sector header when they write a sector?
This is my understanding based on reading the documents and looking at schematics.
I stumbled upon my copy of the documentation for an S100 cartridge disk controller a couple of days ago
and the way they deal with sectors is really simple, they do a seek to a track, read a full sector based on the sector
count from index, then to write since they know they are on the correct track, just write out the whole sector with
new sync bytes and header.
On the RK05, the write gate is activated and a stream of zeroes are written followed by a single one, which is the sync. Then the sector data is after that. It's really simple and that way the drive doesn't have any concept of leader, sync, data, CRC, etc.
That guarantees there is no write splice after the sector header
Exactly. I suppose there will always be a splice if a disk is written on one computer and written again on a drive on another computer, or if the XO in the controller on the same computer has drifted slightly. The splice would be due to tiny differences between the time from when the sector pulse occurs to when write gate goes active. Some splices might be perfect if written on the same computer, controller and drive seconds apart.

I haven't confirmed the following in the controller schematics, but it would be possible to have the controller activate read gate slightly later after the sector pulse than the delay from sector pulse to write gate, so the read would take place after the splice.
 
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Do the DEC controllers rewrite the sector header when they write a sector?
Yes, and thanks for asking. I need to replicate the controller signals to test the emulator. The RK8E controller writes from the trailing edge of the sector pulse up to a tiny gap prior to the next sector pulse. Refer to the WRITE GATE L waveform below.
I stumbled upon my copy of the documentation for an S100 cartridge disk controller a couple of days ago
and the way they deal with sectors is really simple, they do a seek to a track, read a full sector based on the sector
count from index, then to write since they know they are on the correct track, just write out the whole sector with
new sync bytes and header. That guarantees there is no write splice after the sector header
And the RK05 and RK8E do the same. There is a splice immediately following the trailing edge of the sector pulse at the beginning of the all-zeroes data. However, when reading, the read gate is asserted about 83 μs after the sector pulse (85 μs read gate delay minus 2 μs sector pulse width), so while reading, this splice at the beginning of the sector is never seen by the controller.

This timing diagram is how it works. Note that the controller doesn't simultaneously assert Write Gate and Read Gate. They're shown on the same timeline for comparison.
IMG_9898.jpg

The attached pdf shows how the signals are created in the RK8E controller and there's also a copy of a DEC document page that documents this timing. It helped me to understand the schematic first though, to know what they intended in this diagram.
 

Attachments

  • RK05 Read Gate and Write Gate v00.pdf
    1.7 MB · Views: 12
thank you! as you know from looking at the documents, this is all clear as mud in them.

i'd like to build a similar device to read a bunch of weird packs that the museum has (DG 8-sector and burroughs 32-sector)
 
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