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Running a 80486 CPU on the S-100 bus

monahan_z

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For those that have been following Andrew and my efforts to construct new and exciting S-100 bus boards I would just like to present an brief update on our 80386 prototype board.

In 1992 Cyrix introduced the 80486DLC. It was their first serious entry into the mainstream X86 market, and made possible many people's first taste of 486 performance. It was 100% pin compatible with the Intel/AMD 80386. The 486DLC can be described as a 386DX with the 486 instruction set and 1 KB of on-board L1 cache. The 80386's had no on-board cashes. It does not have a math coprocessor however.

Anyway I managed to obtain off eBay a 33MH version and popped it on the board. I found that the board could not attain the 32MHz of the AMD 80386-40 chip but worked fine at 27MHz (the next lowest oscillator I happen to have). Interestingly however even at 27MHz it ran MSDOS software about 10% faster than the 80386 chip at 32MHz. I am currently looking out for a faster Cyris chip as 33MHz may be too close to the limit of the current chip.

A picture of the board with the 80486DLC chip can be seen here:-
http://www.s100computers.com/My System Pages/80386 Board/80386 CPU Board.htm

near the bottom of the page.

BTW as far as I know this is the first published instance of an 80486 on the S-100 bus. I know the DLC was a poor man's 80486, but they were always impressive sides by side with the same clock speed 80386. Don't worry, a "real 80486" CPU board is in the planning stages!

John
 

eeguru

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I found that the board could not attain the 32MHz of the AMD 80386-40 chip but worked fine at 27MHz (the next lowest oscillator I happen to have). Interestingly however even at 27MHz it ran MSDOS software about 10% faster than the 80386 chip at 32MHz.

I'm a little bit confused by this. If you are using a 27 MHz oscillator, you are running the chip at 13.5 MHz. That's no where near the top speed. You need an 80 MHz XO to do that.
 

monahan_z

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Good point, for the S100 bus access, yes, I'm actually dropping the CPU input clock down to 13.5 MHz. The monitor comes up fine BTW its just when I try and load MSDOS I get a Int 6 Invalid Opcode, every time with the 32 MHz oscillator and Cyrix chip. Never a problem with the AMD 80386 or the Cyrix at "27MHz". Both chips also have no difficulty in protected mode.

In the latter case when I access RAM > 16 MG where both chips switch to full speed. Both chips display such RAM fine at 32MHz. I don't have an OS to run is such RAM currently however. So right now I at a bit of a loss to understand where the problem is. I have on order a 33MHz Cyrix chip. I will see how that one behaves.
 

eeguru

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Yes, I saw in the schematic where you are halving the oscillator for S-100 bus access but that's not what I mean. You are actually running the 386 at 7.75 MHz for S100 bus accesses. The 386/486 halves the clock input internally to generate the instruction clock. You are always running the 386 at half the input clock rate. That's why the input clock is called CLK2. It needs twice the clock rate of the processor for generation of the T1 and T2 bus states. A 40 MHz 386 will have an 80 MHz XO. My 20 MHz 386 from 1988 has a 40 MHz XO, etc etc.

The impression I get is you are quoting the oscillator speed as a '386 @ x MHz' where x is the XO speed and that's just confusing to me. You haven't hit 50% of the 386/40's rated speed yet with an XO less then 40 MHz.
 

monahan_z

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Thanks for taking the time eeguru. I suppose its semantics. The actual clock input to the CPU (CLK2) is 2X the Phi clock on the bus. Admittedly the CPU internally splits it in half right away! So when you see advertised an 80386 motherboard rated at 33MHz its really running its CPU internally at 16.5 MHz.

The P1 jumpers control both speeds. In the normal setup for S-100 bus access, CLK1 is divided by 2 (u16A) its output “HALF-CLK1” goes to the CPU via U14 “CUR-CLK” and P9 3-4 as CLK2 @ 16MHz (actual internal CPU speed 8MHz). The Bus Phi signal takes CUR-CLK divides it by 2 (u16B) and via HALF-CUR-CLK and P9 7-8 output (CLK) sends it to the bus Phi signal via u66. This would be 8MHz close to the limit the S-100 bus can normally attain.

When the CPU is accessing RAM above its first 16MG/S-100 bus range (almost 4GB) the CPU runs at its full speed/no wait states. In this case CLK1 input (pin 3) on U14 and output on pin 4 (32MHz) goes directly to the CPU via P9 3-4. The S-100 CLK signal is not used and the memory R/W signals etc. come directly from the CPU itself. In this mode, PC motherboards quote a 32MHz “Clock” which is what we have here even though the internal CPU is really working at 16MHz. I seem to remember the Clock for the 68K series is the same. The next Intel CPU, the 80486 uses a “real” undivided clock, (and actually doubles it internally). I am working on the next board which will use an 80486 BTW.

As to why the Cyrix 80486 won’t get past 27MHz is still unclear to me. As you point out on the S-100 bus it is crawling along at only 16MHz. should not be a problem. Throughout I have always had a problem with the S-100 bus synthesized pWR* signal. From the CPU it lingers on after the S-100 addresses are no longer valid. I have to synthesize a shorter one (u18 ) and am not really crazy with it. May take a deeper look into this. As I said earlier, first I will wait until I get the 40MHz version of the chip.
 
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monahan_z

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I'm actually starting on a "true" 80486DX2 board. In a certain sense it's an easier board since it has 8,16 and 32 bit bus access. However unfortunately you have to do a lot of byte shifting to get the data on the correct output buffers. Will update in a few months.
 

eeguru

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So when you see advertised an 80386 motherboard rated at 33MHz its really running its CPU internally at 16.5 MHz.

No it's not. When you see a 386 motherboard in Computer Shopper advertised at 33 MHz, it's applying a 66 MHz clock on the CLK2 input. It's instruction clock is at a true 33 MHz. It's not semantics. You have it reversed. Even if you don't believe me, look at the data sheet page 126.
 
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monahan_z

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That's in effect what we have done. There is not enough space on the S-100 board for the CPU, support chips and RAM so we have a daughter board connected by a ribbon cable. The "cut-off" where the S-100 bus ends and the daughter board begins is set with an on-board switch. Initially I had it so it could be all the way down to 0H in RAM (now its >16M). You normally want to have some overlap so other S-100 CPU's disk controllers ROM's/BIOS etc can share a common area. Because the MMU is the 80386 is so powerful, the address range so large, I just figured protected mode users would ignore the first 16MG's.

Our best current daughter board is 32MG. We have a 64MG static one in the works, but I'm looking for somebody to do a proper GB DRAM board. It's above my pay scale!
 

monahan_z

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As to the IBM 386SLC, the max clock speed was 25MHz. hard to find because they were used only by IBM in some of their laptops/PS2 boxes.
Also SMD pins so could not swap in the chip on this board.

Thanks for the suggestion however.
 
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