Scambled eggs and address lines...

[leeb]

Okay... see if you can follow me here.

I am attempting to repli-create the 35-pin 1Mb(256kx4x8 ) RAMS for my 2810s and similar panasonic laptops...
and I have been having trouble with routing, pretty much everything!
So... I have 4 chips on each side, and unlike the original RAMs (which were rung out for this purpose), I am 'adjusting' things.

I am not following the normal routing of data0-7 to pin(d0-7), but have 'mixed' them to get shorter/less complicated traces, which has kept me down to 3 layers so far...


But, what about the ADDRESS lines (A0-A8.. total of 9 )?
Being as they are dynamic RAMs, would having the addresses 'scrambled' by not following the normal binary pattern cause refresh issues?
A total of 8 lines gives 0-255... so no matter what order they are in, there will still be only 255 possible combinations, just not 'linear'.

Any thoughts? :twisted:

Uh oh... the 666th post!

 

[Chuck(G)]

RAS and CAS on 8 address lines only gives you 65K worth of addressing. Have you missed a line? A 41256 DRAM for example, has 9 address line (A8 is pin 1), giving 256K worth of addresses.

 

[leeb]

No... there are actually 4 CAS# lines (0-3)... each CAS# goes to a pair of chips...

:bomb: Looking again I see I DID forget A8... for a total of 9...

OP adjusted... :D

Here is a sample of what Ive managed to complete so far... but havent even BEGUN on the back level yet...
(thus, the ratlines)



So far, the address lines havent even been assigned pins, let alone layed out...
I have been using FREEPCB for this and in general it is working well... but I have experienced an issue that irritates the unholy hell out of me, so I am attempting to learn a 'company-supplied' package in hopes that it will work better.
So far, Im still on FREEPCB.

:D

 

[Chuck(G)]

There's always KiCAD--and I think that Eagle offers a freeware version with reduced capabilities (not sure about the maximum board size).

Otherwise, the address line and data line ordering shouldn't matter. On "smart" chips (RDRAM, DDR, etc. ordering does matter, however)

 

[leeb]

The absolute LAST thing I want to use is something with 'reduced capabilitites'... I am pissed enuf as it is...
I have one from SunStone (or somesuch... PCB123) but it is driving me absolutely BONKERS... It seems that I have to create EVERYTHING from scratch... it is NOT 'intuitive'... and have been working to learn it since the last edit on the previous post... actually before.

Thanks for the confirmation RE the address lines... I believed that to be true but hearing it helps!

... and I have a headache now...

:D

 

[pearce_jj]

Eagle offers a freeware version with reduced capabilities

The free version is 80x100mm routable area, 2 layers (top and bottom), 1 design sheet.

 

[leeb]

The free version is 80x100mm routable area, 2 layers (top and bottom), 1 design sheet.

but...
I need a routable area of 4 in x 0.6 in... would it fit?

I dont know if it can be routed with only 2 layers... the image I put up already has 3 (one not yet used - back)...
Wouldnt hurt to look into it I suppose...

 

[per]

The IBM 5160 has A14 at A8 and A8 at A9 and so on for the motherboard DRAM, so I would guess it's ok. As long as every address is refreshed often enough it shouldn't matter where the logical addresses map in the physical chips.

IBM didn't do it to reduce complexity, but to add support for the Intel 2118 16Kx1b DRAM chips. In the end they used the 4164 64Kx1b instead, but support for the earlier still remains if you alter some of the motherboard jumpers. For reference, the Intel 2118 was a 5V-only version of the 4116.

 

[leeb]

An Update

An Update

Well, I have been 'tightening and tweaking' what I already have done, and inserted the 4th layer (#2 internal) 'pretty-much exclusively' for the address lines.
I am attempting to run the address lines 'true' so far... and have been 'somewhat' successful...

So far, I have only a few more (A0-A3) to finish up and the FRONT will be done. AT THIS POINT the back has NOT been touched. In fact it is moved 'off the board' to prevent the issue I go bonkers about...

Looks like:



I can only hope that I am applying enough 'forethought' to get the back done too.
:D