Single Instruction Computer Architecture

[Thrashbarg]

So I've gone mad.

I've written an emulator for a SIC (aka OISC, but One Instruction Set Computer isn't right) and will implement it in hardware in the next few days or weeks, whichever happens first...

The idea is the instruction it executes is Subtract and Branch if Negative. Each instruction is three memory addresses, A, B and C. In my specific implementation, B is subtracted from A, the result stored in A and if the result is negative, jump to location C. B and A are pointers, so the actual operation happens elsewhere in memory.

This is horribly inefficient. So I reduced the instruction to two memory addresses, A and B. C usually points to the next instruction anyway so there's no point in having that sort of redundancy (it's not an IBM 650). The machine itself is therefore a subtraction machine.

To perform a conditional branch, a specific memory mapped register is used. When A points to this location, the address directly at B is loaded into it, rather than being subtracted. This saves a lot of hassle. If you want, you could say that when A points to the register, A becomes an op-code and the operand is B (so, very technically it isn't quite a SIC).

When the register is loaded, the instruction following is executed as normal, however if the result is negative the program counter is loaded with the data at the register and the register is set to all 1's. When it is all 1's, all instructions are treated as Subtract, not Subtract and Branch.

So it's rather tricky in concept, but shouldn't be that difficult to implement in hardware.

The emulator and some binary files with source are here
http://kaput.homeunix.org/~thrashbarg/oisc/oisc-emulator.tar.gz

There are two example files, fibonacci.bin and e.bin. They calculate part of the Fibonacci series and the first 1000 digits of e - slowly.

The emulator implements a 16-bit version of this architecture with 32k words of memory. The register and console I/O ports are at the top of this memory space. When the Program Counter is 32767 (0x7FFF) the emulator terminates.

Also, on my 2.4GHz Celery it executes at about 25MIPS and takes a good few minutes to calculate e. TTL being TTL, my hardware implementation will be somewhere around 1 to 2MIPS... This is probably why no one bothers with this architecture.

Maxim Dallas do produce a Single Instruction microcontroller, the MAXQ, however it's a move machine. To achieve some sort of computational ability, there is a memory mapped ALU and registers.

edit: Yes, there is another emulator out there for an OISC, however I wrote this one as a concept for a hardware implementation

 

[Mike Chambers]

wowww... impressive project! keep us posted.

 

[Thrashbarg]

Righto, I'm sure you're all on the edge of your seats in anticipation :roll:

So far I've got three cards developed. One controls the overall operation of the computer, one does the subtraction, and one holds RAM/ROM with a programmer so I can load and store data to memory through my PC's parallel port.

The control card has the clock, a smallish array of logic (for a TTL computer), the address pointer registers and the program counter. The registers are A, B, C and PC. A and B are loaded from the instruction, C is loaded instead of B if A is 0xFFFF, and PC is the program counter.

The subtraction card has two registers. These hold data pointed by A and B so the result can be put back onto the bus and stored.

The basic instruction cycle is this:

1) Load A from (PC), increment PC.

2) Is A 0xFFFF (pointing to Register C)?
YES: Load Register C. Reset instruction cycle.
NO: Load B, Increment PC.

3) Load A data from (A).

4) Load B data from (B).

5) Store result to (A).

6) Result negative (MSB true) and Register C loaded?
YES: Load Register C into PC. Reset instruction cycle.
NO: Reset instruction cycle

One thing about this architecture is it strays from some ideas used in RISC. Namely one instruction per clock cycle, pipelining, and so on.

Currently I'm running it at 0.6MHz.... yea, it's slow. I've got a 3.6MHz and 8MHz crystal but it goes nuts when I try them. Seems my high speed digital logic design isn't very good

Pics, circuits, maybe a video coming.

Edit: I just rearranged part of the clock circuit and it now works at 8MHz, probably more, but I don't want to push my luck