Well, in fact it is a IBM 5162 XT/286 motherboard what I have right here, but it is the same for the purpose. I'm trying to understand "the magic" that makes 8 bit cards work in this 80286 motherboard. How is a 16 bit access cycle splitted into two 8 bit cycles? I can't find any reference in the schematics on the Ref Tech manual...
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Trying to understand IBM PC/AT 80286 8-bit bus access
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eeguru
Veteran Member
It is up to the chip set to handle this as there is no size pin on the CPU itself. The chip set must both handle steering of the lower ISA byte to the upper CPU byte in the case of 8-bit odd address access and it must break the bus cycle into two while injecting waits in into the CPU and latching the first lower cycle into a holding latch.
From the ISA perspective, as long as a card does not assert IO16n by mid-way through the second clock cycle after strobe assertion, the end device is assumed to be 8-bit. At that point, the steering logic would need to latch the lower ISA data byte, keep injecting waits to the cpu, while optionally performing a second ISA bus cycle access based on BHEn and A0. Then it would present the full 16-bit value to the CPU during the end of the second chip set initiated cycle.
From the ISA perspective, as long as a card does not assert IO16n by mid-way through the second clock cycle after strobe assertion, the end device is assumed to be 8-bit. At that point, the steering logic would need to latch the lower ISA data byte, keep injecting waits to the cpu, while optionally performing a second ISA bus cycle access based on BHEn and A0. Then it would present the full 16-bit value to the CPU during the end of the second chip set initiated cycle.
maxtherabbit
Veteran Member
the way I understand it:
chipset (or bus master?) asserts SBHE# when it puts the address on the bus
when the target device decodes the address, if it is a 16-bit target, asserts MEMCS16# or IOCS16# (depending if the access is to a memory location or I/O port)
chipset (or bus master?) performs a word transfer if one of the '16' signals is asserted, or splits transfer into 2 8-bit cycles otherwise
chipset (or bus master?) asserts SBHE# when it puts the address on the bus
when the target device decodes the address, if it is a 16-bit target, asserts MEMCS16# or IOCS16# (depending if the access is to a memory location or I/O port)
chipset (or bus master?) performs a word transfer if one of the '16' signals is asserted, or splits transfer into 2 8-bit cycles otherwise
tipc
Banned
This may be of value:
https://www.amazon.com/Interfacing-Personal-Computer-Lewis-Eggebrecht/dp/0672227223
I actually have a copy but I'm in NJ. The first edition is available on archive.org, but it only covers the 5150 I believe.
https://www.amazon.com/Interfacing-Personal-Computer-Lewis-Eggebrecht/dp/0672227223
I actually have a copy but I'm in NJ. The first edition is available on archive.org, but it only covers the 5150 I believe.
Stone
10k Member
I have this one:
And there's always:
https://archive.org/details/Peter_Norton_Inside_the_IBM_PC_Revised_and_Enlarged
and,
https://archive.org/stream/Peter_No...side_the_IBM_PC_Revised_and_Enlarged_djvu.txt
and this which is an exact reproduction:
http://chiclassiccomp.org/docs/cont... Inside the IBM PC - Revised and Enlarged.pdf,
And there's always:
https://archive.org/details/Peter_Norton_Inside_the_IBM_PC_Revised_and_Enlarged
and,
https://archive.org/stream/Peter_No...side_the_IBM_PC_Revised_and_Enlarged_djvu.txt
and this which is an exact reproduction:
http://chiclassiccomp.org/docs/cont... Inside the IBM PC - Revised and Enlarged.pdf,