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update on my TRS-80 Model 100 CP/M rig

T

Twospruces

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It has been some effort, but I am really enjoying the outcome.
I have what I would call a pretty unique CP/M system here.

Starting with a stock TRS-80 Model 100, I have....

* firstly developed a plug and play SRAM card that enables 64k RAM mode + a 3.5MB ramdisk - REXCPM
* supported Mr. Avery in the development of M100 CP/M - a port of CP/M 2.2 intended to leverage said REXCPM

(all of this is documented at the M100 Wiki: http://bitchin100.com/wiki/index.php?title=REXCPM)

so, to this point, what you get is an 80C85 based CP/M rig, on a 40x8 LCD. Nice!

Then, taking it a bit further, recall some earlier discussion about the NSC800 CPU - aka Z80 in 8085 clothing.
* I now have a small adapter board that supports running the NSC800 in the M100. 2.5MHZ Z80.
* (and it turns out you need to change the embedded ROM a bit to handle certain changes to the interrupts)
* I found a way to drive Tx TTL serial data out the somewhat underused BCR port as well, freeing up the sole RS-232 port for other uses. (my "BCR Hack").

And then lastly, to expand the video capabilities
* I have a version of the Geoff VT-100 terminal, modified just slightly to make it work better with M100. This converts serial TTL console to VGA.

End result-
A TRS-80 Model 100 running "Z80" with an external 80x24 LCD and a fast internal SRAM disk for CP/M 2.2.

Pics:
Here is the view of the main board. You can see my NSC800 adapter and the adapter for a revised main ROM.
20201004_075708.jpg

Closeup of the NSC800 adapter:
NSC800.jpg

Closeup of the main ROM adapter with the slightly revised Microsoft main ROM.
20201004_075734.jpg

And finally, the complete system, which happens to be running Turbo Pascal 3.0. You can also see the VT100 adapter converting console serial data to VGA.
20201004_081229.jpg

So far it is running flawlessly. Some of you may recall, as pointed out in the Microsystems Sept 84 article on making NSC800 adapters for 8085, that the NSC800 has a short opcode fetch cycle. In the M100, no wait state is needed; everything seems fast enough to keep up.

I have no problems running whatever CP/M software I like it seems.

In truth, the system works with either the stock 80C85 or the NSC800. I guess there is only a minor advantage in having the Z80 compatible under the hood; much of the software is 8080. Still it was a challenge to do, and I'm happy with the result.

REXCPM and M100 CP/M are available. I'm working on an NSC800 adapter that is good enough to share or offer as a kit. I've posted an interim schematic and layout at the same wiki mentioned above as well.

None of this is particularly hard to do. The biggest part of the conversion is the removal of the 80C85 and the addition of a socket.

Cheers, comments welcome.
 
Nice work, looks amazing.

I wonder how this would work with the M100 Video/Disk adapater.
 
whartung said:
Nice work, looks amazing.

I wonder how this would work with the M100 Video/Disk adapater.
Click to expand...

Good question indeed. The DVI attachment would be really a natural for a CP/M implementation.
The DVI video portion certainly acts like a terminal. And the disk acts like a normal floppy controller.
It would be very different from what is shown here though.

And, the other think is RAM. The DVI does not address the limited 32k RAM in the stock M100.

So, REXCPM provides 4MB of SRAM, divided between RAM disk and RAM used for system memory.
 
Minor update!
I have implemented a 2x speed up board .. aka CPU adapter... for both the 80C85 and the NSC800.

With either of these boards you can run at 4.9 MHz.

The board are just slightly larger than the CPU and easily plug into the socket of the 80C85.

It is kinda fun to run 2x faster. Should have been that way to begin with!

I'll have to post some photos.

In experiments I was able to run over 6MHz, but generally you need faster system rom and ram.
The video drivers fail around 8 MHz, which really was the limiting factor.
5MHz was a nice tradeoff.
 
Well, in a nutshell, you need to change the timing circuit. You have to drive the cpu with a faster clock but maintain a 2.45 MHZ clock on the CLK output signal.

On an M100, to double the speed to 4.9MHz, you also need faster RAM and a faster main ROM. I believe a T102 already has gast enough memory.

I made an adapter board to do changes to the CPU
To install it you need to, for this design, to desolder the CPU and install a socket. Then the adapter board can plug in, with the CPU soldered into the adapter.

I'm thinking about an alternative approach though, where you just clip the X1 and X2 pins, and the CLK out pins. That way you might be able to just piggy back a small board with the crystal circuit on it.

You interested it trying it out Mike? I can send you some parts.

You can use one of your 27C512 adapter boards for the faster main rom.

For RAM, REXCPM does that nicely. Otherwise as you can imagine getting faster system RAM in an M100 can be a bit of a chore.

My only use case for NSC800 is in a dedicated CPM machine.

One last comment. 4.9 MHZ is nice ad it is 2x. But the ram and main rom seem to support up to 4MHz. So that could be an approach. A tidy 60% improvement.
 
This is amazing! I currently have a spare Model 100 board which would be a perfect candidate for trying this... I already have REX CP/M.
Cheers
Michael
 
Twospruces said:
Current bumped from about 60mA to about 85mA. Worth it for me ;).
Click to expand...
I've actually been working on a carefully designed 5MHz upgrade board for the TRS-80 Model 100.

My first 5MHz upgrade designs ran into a challenge on some or all M100s. Here's what I found.

1) the "stock" main ROM chip is quite slow - 600nsec - and as such I think one must replace the main ROM with a faster PROM of some kind. Lots of ways to do that.

2) the "stock" system RAM modules can be quite slow also. Anything that is 200nsec or faster seem to tolerate running at 5MHz. However the earliest M100s were shipped with RAM modules that have 250nsec SRAM parts. Those are just a tad slow.


So, what to do?
One could replace the ram with faster RAM. It's actually a bit of work because there is always one or more RAM module soldered in. So if you have to pull it, or otherwise modify the ckt to disable it, that is a fair bit of work.

A nicer way to go would be to find a way to make the built in memory tolerate running at 5MHz.
Is 250nsec an issue? Well the fastest Read cycle on the 80C85 is 3 clock cycles, which at 5MHz is about 600 nsec. So maybe a bit tight.
If we can chip-select early in the read cycle perhaps there is enough time.

Well, it turns out that a pretty simple change can allow us to change the main timing signal that interfaces the SRAM. (A* signal).
By advancing the timing by about 100nsec, you can give enough breathing room to the slowest SRAM chips so they can respond correctly.

My latest design is working very well and saves quite a bit of power.
What it is, is a small board that piggy-backs on the CPU. It supplies the needed CPU clocks for either stock 2.5Mhz or turbo 5MHz operation.
It also generates the one modified timing signal A*.

* increases the M100 power supply current from ~50mA to about 70mA
--> of the 20mA of extra current, 5mA is due to the new crystal oscillator ckt alone.
--> the system itself running at 2x clock uses only about 15mA extra.
* works with the stock SRAM modules
* does require that the stock system ROM be upgraded to a faster PROM (like 27C256)
* requires 2 cut tracks and 2 wires, as well as about 10 signals piggy-backed from the CPU

Anyhow it has been a fun little project to dig into and optimize.

Yes, 70 mA is 40% more than 50mA, but I think for usability it is worth it.
You can combine this mod with my "fast hardware scroll" modified system ROM image to really speed things up.
Especially since you have to swap the ROM anyhow.


I'll eventually post some info at bitchin100.com that will provide instructions and access to a board.

cheers
 
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Slight necroposting to ask if you've found any software that the 5MHz upgrade interferes with? I'd rather do as little SMD soldering as possible, so if I don't need the switchability, I'll just go for the simpler fixed-speed upgrade.
 
This thread starts out as thread about M100, CP/M, 5MHz 2x speed and then NSC8000.

then it discussed an improved 5MHz upgrade that is focused on 80C85. Regardless of CP/M.

So I think you are asking about just a general 2x speed upgrade for the M100. That is well developed now. "Done and used regularly".

Yes, you can upgrade a stock M100 to 5MHz. You can even safely use the really slow early 8k ram modules.

In terms of software compatibility, yes tsdos actually has some sensitivity. So it isn't 100% but I still run 5MHz as a default. If I encounter an issue I can switch back to 2.5 MHz.

I have 2 adapter PCB designs completed. Both are switchable. I'm convinced that switchable is the way to go.

1. A board based on 74HC logic
2. A board based on a 3.3V CPLD.

The latter is harder to make but it saves about 5mA. Board 1 is surface mount and solders to the back of the 80c85. The clock cut has 0805 smd to solder so is a bit of work.

Both designs, after much optimization, work with even the slowest M100 main RAM modules. The installation requires 2 tracks cut on the main board, which are easy to repair and reverse.

I really should document the entire thing.

I use 5MHz in my 2 bench test boards for building REX#, and in my regular use machines. .. Both T102 and M100.
 
oktology said:
Slight necroposting to ask if you've found any software that the 5MHz upgrade interferes with? I'd rather do as little SMD soldering as possible, so if I don't need the switchability, I'll just go for the simpler fixed-speed upgrade.
Click to expand...
The thing about the fixed upgrades... not sure I did a design that includes three advanced timing A* signal that enables the slow RAM to work.

Should not be too hard though.

Yah, the fixed upgrades are easier to build because you can swap the onboard crystal.

Plus with fixed you can run into software issues, making the switchable design more flexible.
 
Gosh, I really need to update this page: https://bitchin100.com/wiki/index.php?title=5MHz_Upgrade_hacks


Bit more info on 5MHz adapter boards. Here are some small layout pics with descriptions. These are "current".

1. Fixed 5MHz 80C85 adapter including A* circuit. Used for stock M100/T102 upgrades, and supports old/slow M100 ram modules.

Fixed_5MHz_Astar..JPG
As you can see, two 74HC smd parts. Pretty simple, works well, but you run the risk of wanting to run at normal speed and being unable to.

2. Fixed 5MHz NSC800 adapter. There is a whole set of info here on this conversion: https://bitchin100.com/wiki/index.php?title=NSC800_Conversion

Fixed_5MHz_NSC800.JPG
Some SMD soldering, new crystal, etc. More surgery, but fun for CP/M. Z80!

3. Switchable 5MHz 80C85 adapter including A* circuit, based on 74HC SMT.

Switch_74HC_5MHz_Astar..JPG
Pretty dense layout, lots of small SMD 0805 + a tiny 5 pin unbuffered inverter for the crystal ckt. Tougher to make, but flexible.

4. Switchable 5MHz 80C85 adapter including A* circuit, based on 3.3V CPLD.

Switch_CPLD_5MHz_Astar..JPG

The best design, very very flexible, but a stretch for the hobbyist. I used this one because it is the lowest power adapter.
on the right, there is a JTAG circuit that is detachable, that is used to program the CPLD. Since the CPLD has a lot of resource unused,
I have lots of extra I/O pins to do custom things. Most are not used.


Any fast M100 usually needs a faster main ROM. Early production used slow PROMs, later ones are faster.
If you need a faster main ROM, there are lots of ways to skin that cat.
 
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Whoa, thanks for all the info! I’d love it if you updated the documentation and the page on Bitchin 100, I didn’t realize how much the design had evolved since what’s listed there!

I’ve been burning PROMs for vintage synthesizers (most of which didn’t originally come with socketed ROMs) for a while, so replacing the system ROM with a faster chip is no sweat.

I was asking specifically about if it affects M100 software, I’m not quite ready to take the plunge into CP/M. Do you know if the patched version of TS-DOS with the delay built in affects that?
 
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