A bit of curiosity here--how closely is the original XT hardware emulated? Can I, for example, vary the memory refresh interval by reprogramming the 8254 (and is there a refresh flag that's readable?).
Due to (very tight) firmware constraints, some key mainstream aspects of the architecture have been retained, whilst other parts have been 'simplified'. I guess you could think of this as a 'lean' implementation
Your example would not work on this hardware, as any read from Port 41h would have no effect and writes to the same would be ignored..
Merely curious, but why would you want to vary the refresh interval anyway? Everything I've read about the memory refresh timing indicates that it is probably best left alone?
Do you emulate the 3237 and 8259 chips?
If by 3237 you mean 8237 DMA then no, well at least not at this time.
Currently testing the 8259 PIC functionallity at present.
If I were to pass you the image of the Landmark XT POST ROM, would it run successfully?
It would probably fail, due to lack of (any kind of) support for the FDC hardware (but it does fail with 'drive not ready' error when anything other than drive 80h is accessed via INT 13h), among other things..
You see, the supported ROM BIOS functions are in fact serviced via native algorithm(s) (
including non-standard INT 33h!). This provides two fairly major advantages:
1.) From the users point-of-view: Enables accelerated BIOS function execution.
2.) From my point-of-view: Allows more efficient use of the available firmware capacity.
Or is this more a matter of supporting XT functionality at the BIOS level?
While there is a strong emphasis on the BIOS-level functionality, there is also at least reasonable support at the I/O register level i.e. port 60h read keystroke etc
I have a partly-compiled list of supported BIOS/registers, though it is a work-in-progress. Will try to clean this up and post it when I have free time.
Regards,
Valentin