Recent content by bladamson

Yeah, my assumption is that it's straight through. I am assuming they're just looking for a 1:1 current balun and there isn't any voltage matching going on there, since I assume the impedance is the same on both coax ends. Presumably all they are doing is using the transformer to convert the...

Hitech C is pretty good. Almost-but-not-quite ANSI. You can run it on a modern OS with zxcc as a cross compiler, or native on CP/M.

If you go with the RC2014, just remember that the backplane has 40 pins per position, but some of the cards only have 39 pins per position. If you don't realize this and plug the card in 1-pin off, you'll destroy something. In my case it was the Z80 CPU. It's a cool project and I have nothing...

The RC2014 seems to be inexpensive and well-regarded, although it has some design shortcomings.

The terrible not-release of the Z800 really put a nail in CP/M's coffin I think. PCs were in the right place at the right time to pick up the ball that Zilog and DR dropped.

I used an old scsi enclosure for mine. All the scsi stuff still in there, so easy to convert back for the next guy. It had some knockouts in the back for audio connectors (I assume), so I just punched one of those out and hot glued the 'weazle in there.

I think there were two different keyboards. One may have been rubber dome? I can't remember. One of the more serious Tandy guys will chime in I am sure.

The switches go bad sometimes. They can be taken apart and cleaned, although it's kind of a pita. I think I'd try a bunch of deoxit and some exercise before I went to all that trouble, especially if it's only one key that's bad.

Be there or be square! It's a great show, and a great community! (This message brought to you by Heathkit Gang!)

If your CPU isn't running right, it's probably never getting to the instruction that polls the keyboard port and triggers the wait state generator. I am sorry to keep beating the proverbial dead horse, but you have verified that the CPU is resetting correctly at power-up, right? It's unclear...

No, wait a minute. I am full of crap. It looks like the firmware reads a port when it wants to write to video memory. That read sets one of the latches in U428, and then then next vertical sync pulse generates a single NMI and resets those latches. So I don't think we should be seeing a ton...

I still don't understand why M1 isn't running though. Even if it's in some kind of interrupt handler loop, it ought to be asserting M1 every time it starts a new instruction, right? On the schematic I am looking at, M1 isn't even connected to anything, though, so there shouldn't be anything on...

If we're talking about the z80 on the terminal board (not the one on the cpu board), I am 95% sure that one of the interrupts is used to signal the CPU when it's safe to write to video ram without causing display artifacts (even though with the stock rom it has display artifacts anyway, lol). I...

I think NMI may be connected to the vertical blanking interval, but I don't remember for sure. It's in the manual, but I'm not in a place where I can check it atm.