30 pin SIMM memory for RC2014 z80 Processor

[Plasmo]

I believe both expanded RC2014 bus as well as 80-pin RCBus have WAIT and REFRESH signals, but the added connector space makes it difficult to fit the dual socket design on the 50x100mm format. Same design with single SIMM30 socket should fit, however.

I tried removing the onboard Z80 and replacing it with external Z80. It will boot, but unable to run program in DRAM. I may not have wired WAIT or REFRESH correctly. However, I like to know the motivation for moving onboard Z80 to external Z80. Are you shooting for multiple Z80 sharing a common 32meg RAM?

 

[-N2]

I believe both expanded RC2014 bus as well as 80-pin RCBus have WAIT and REFRESH signals, but the added connector space makes it difficult to fit the dual socket design on the 50x100mm format. Same design with single SIMM30 socket should fit, however.

I tried removing the onboard Z80 and replacing it with external Z80. It will boot, but unable to run program in DRAM. I may not have wired WAIT or REFRESH correctly. However, I like to know the motivation for moving onboard Z80 to external Z80. Are you shooting for multiple Z80 sharing a common 32meg RAM?

Not everyone can source the specified PLCC-packaged z80 CPU.

 

[Plasmo]

PLCC44 Z80 are readily available from eBay. They may be relabeled parts, however. I’ve purchase enough parts across half-dozen sellers to know they are always CMOS Z80 and capable of 25Mhz operation, in fact, most of them will run at 30Mhz, some to 33Mhz. They are more expensive than DIP Z80, about $3 each in quantity of 10.

 

[-N2]

PLCC44 Z80 are readily available from eBay. They may be relabeled parts, however. I’ve purchase enough parts across half-dozen sellers to know they are always CMOS Z80 and capable of 25Mhz operation, in fact, most of them will run at 30Mhz, some to 33Mhz. They are more expensive than DIP Z80, about $3 each in quantity of 10.

To be frank I trust the sellers on AliExpress more than any eBay vendor I have ever dealt with.

 

[Eudimorphodon]

To be frank I trust the sellers on AliExpress more than any eBay vendor I have ever dealt with.

They’re very often the same people.

 

[Plasmo]

Since I’ve never purchased items from Aliexpress, I’m not in the position to judge. I do know aliexpress’ prices are cheaper than eBay. What I like about eBay is its return policy. If parts didn’t work, I’m guaranteed to get my money back, so I always test parts I received right away and ask for refunds for defective parts. I’ve exercised that return policy once in a while and never disappointed. The other source I used is UTSource.net. They also have pretty good return policy and I’ve exercised it and satisfied with it. In general most used parts are good except 6502 and CPLD.

 

[Plasmo]

One application with large RAM is loading video data into RAM and displaying the video at reasonable frame rate. This is a snippet of “BadApple” running on a 128x64 OLED screen via I2C interface. The video data is 3.1 megabytes that takes many minutes to serially loaded into RAM. It is played back at about 12 frames a second. This is a visual way of checking RAM integrity.
Bill
Hmm, not able to attach video?

 

[-N2]

One application with large RAM is loading video data into RAM and displaying the video at reasonable frame rate. This is a snippet of “BadApple” running on a 128x64 OLED screen via I2C interface. The video data is 3.1 megabytes that takes many minutes to serially loaded into RAM. It is played back at about 12 frames a second. This is a visual way of checking RAM integrity.
Bill
Hmm, not able to attach video?

Can your board work with the Z80Ctrl board? The ctrl board has an AVR Microcontroller on it to act as a pony processor to load SRAM on a companion support board. Such a model enables a system with only RAM and no ROM. Is there enough space in the CPLD to fill the bottom 32KB of address space with the other 8MB of DRAM?

 

[Plasmo]

I don’t have latest Z80CTRL, so I don’t know if ZRC can work with it. ZRC has no ROMWBW memory, but a small lookup table in CPLD that serves as ROM. This ROM loads program from CF disk to RAM and then jump to it. Since CPLD is programmable, I can easily disable the ROM function and wait for Z80ctrl to do its thing. Top 32KB of ZRC is common memory, the bottom 32KB is banked memory, one of 256 banks can be selected to be the bottom 32KB.
Bill

 

[-N2]

This is a solved problem, as of October 1987 at least. Page 2 of https://archive.org/details/80-micro-oct-1987-upgrade-your-m-4-to-320-k/mode/1up has the necessary circuitry to extend the Z80 built-in refresh to 256-cycle. The article text describes its operation. There are other mods for the 4 and 4P by others that do similar things. The essence is to count 128 cycles and toggle a bit each set of 128, and that becomes your 8th bit. It doesn't even have to be "in phase" with the Z80's refresh counter; it just needs to toggle every 128th instance of the refresh signal.

I built a mod very much like that one myself, expanding my Z80-based TRS-80 Model 4 to 320K. As far as I know all 256K DRAM chips are 256-cycle.


There have been many schemes over the years to bank switch. As Plasmo said, 32K pages are common and well supported. The TRS-80 Models II and 4 both do 32K pages using two different schemes; the Model II uses a distributed write-only I/O port for page select. Plasmo has several designs for this sort of thing that are well tested.

It'll be an interesting project for you to solve that yourself, though; don't think that just because someone else did it a certain way that you can't learn from doing it a different way.

I wonder if a super crude hack of flip/flopping the 8th bit clocked from the LSB would work to interleave the refresh cycles.

 

[-N2]

I don’t have latest Z80CTRL, so I don’t know if ZRC can work with it. ZRC has no ROMWBW memory, but a small lookup table in CPLD that serves as ROM. This ROM loads program from CF disk to RAM and then jump to it. Since CPLD is programmable, I can easily disable the ROM function and wait for Z80ctrl to do its thing. Top 32KB of ZRC is common memory, the bottom 32KB is banked memory, one of 256 banks can be selected to be the bottom 32KB.
Bill

Heh I made an 80-pin carrier board for an Arduino Mega2560 if you'd like to try it. I'll have to dig up the design files; I think I included a SIP header for this uSD card adapter https://www.pololu.com/product/2587 I recall the purpose of this abomination was to have enough GPIO to monitor all the bus signals, while preserving the ability to serve as a Pony processor to aid in bootstrapping a ROM-less system.

 

[-N2]

I converted the prototype SIMM30 tester I built a month ago into a Z80 SBC for RC2014. It is a revised ZRC where onboard 2meg DRAM is replaced with a dual SIMM-30 socket. It is a 4-layer 50mmX100mm pc board; Z80 is running 14.7MHz and it is RomWBW ready. I purchased a pair of 16meg SIMM30 for this board, but memory is currently limited to 8 megabyte because the byte-wide bank register can only hold 256 banks of 32KB bank. To go to 32MB, I need 10-bit bank register that writes 10 bits bank values in one I/O operation.
Thinking about an application that will use 8meg of RAM...

Would it be possible to cheat by asserting the high byte during an I/O write?
Well perhaps I should first ask how you are converting the 15-bit linear address into the two-part Ras/Cas addressing for the SIMM30 memory. Is it as simple as using the first 12 Least significant bits for the first half of the cycle, and then applying the remaining bits with some additional bits for bank selection?

 

[Plasmo]

I think using contents of regB as high byte is a pretty good idea. It will works, but is not backward compatible with existing software, including RomWBW. However, very few existing programs deals with this kind of bank register, so software incompatibility may not be a big deal.

Conceptually for 8 meg RAM, I have 256 banks of 32KB per bank, so row addresses are A0-A11, and column addresses are A12-A14, BANK0-BANK7. This will uniquely access 8 meg of RAM. In practice there are interleaving of addresses and BANKs because I want to accommodate 1meg, 4meg, and 16meg SIMM30 without changing hardware or manipulating jumpers.
Bill
Edit, by “high byte”, I assume you mean using “out (c),r” instruction where contents of RegB is placed on high addresses A8-A15.

 

[Plasmo]

I wonder if a super crude hack of flip/flopping the 8th bit clocked from the LSB would work to interleave the refresh cycles.

Most DRAM support cas-before-ras refresh, so the logic in CPLD generates a cas-before-ras refresh in response to Z80’s RFSH signal. So addresses are don’t-care.

 

[-N2]

I think using contents of regB as high byte is a pretty good idea. It will works, but is not backward compatible with existing software, including RomWBW. However, very few existing programs deals with this kind of bank register, so software incompatibility may not be a big deal.

Conceptually for 8 meg RAM, I have 256 banks of 32KB per bank, so row addresses are A0-A11, and column addresses are A12-A14, BANK0-BANK7. This will uniquely access 8 meg of RAM. In practice there are interleaving of addresses and BANKs because I want to accommodate 1meg, 4meg, and 16meg SIMM30 without changing hardware or manipulating jumpers.
Bill
Edit, by “high byte”, I assume you mean using “out (c),r” instruction where contents of RegB is placed on high addresses A8-A15.

Yes that last bit about RegB on A8-A15. Thinking about it some more,

A0-A7 + 4 LSB bits from RegB during Ras
A8-A14 + 4 MSB bits from RegB with A15 placed as the MSB during CAS is a clean way to handle the different SIMM sizes in software.
With anything less than a 16MB SIMM the A15 pin isn't a factor, it might as well be a chip select or output enable.

 

[-N2]

With an additional latch, the A15 line might be used to toggle between two independent banks. Where one set of bits from RegB is used to control the lower 32K and another for the upper 32K. I am not aware of any existing code that could use all that, but it seems technically feasible. Who knows perhaps set page FF or 00 to disabled to bypass the DRAM and allow something else on the bus to occupy the address space.

 

[Plasmo]

The existing 128 macrocell CPLD is 100% utilized, but there are larger CPLD except they are very difficult to find. Maybe 2 CPLD, or maybe moving some functions out of the CPLD such as the serial port. Alternatively, since CMOS Z80 will run reliably to 3.5V, it can also work with many FPGA without the pesky voltage translators. Sky is the limit once we cross over to FPGA.

 

[-N2]

Mixing legacy 5-volt systems with the newer low-voltage stuff is when hobby projects become less enjoyable.

 

[-N2]

This might be doable with a large bank switchable memory card,

 

[-N2]

Most DRAM support cas-before-ras refresh, so the logic in CPLD generates a cas-before-ras refresh in response to Z80’s RFSH signal. So addresses are don’t-care.

With 5-volt CPLD chips becoming harder to source, how many 74-series chips would it take to build this DRAM interface circuit?