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8-Bit IDE Controller

per said:
Please explain. As of I see from the datasheet, the output will allways be either H or L, not indeterminable. DMA is just like another processor only capable of reading and writing memory, and it operates the adress and data lines exactly the same way the normal CPU does. As of I see form your schematics, there will allways be a valid /CS signal just depending on the adress on the adress lines.
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Hi! The ROM will only appear in the memory map when the signals when the ROM chip select signal goes low (/P=R) on the P side match those on the R side and /G is low. If the ROM enable jumper is not present, the pull up resistor will pull /G high and keep it there. The ROM chip select signal will never be produced. If the ROM enable jumper is there and DMA is active (AEN=high), the ROM chip select signal will never appear regardless of what is on the P or R sides. If the ROM enable jumper is there and DMA is no active (AEN=low) then AEN will pull /G low and when P=R the /P=R signal will be generated causing the ROM chip to be selected.

In other words, there are three conditions which must be met for a ROM chip select signal; 1, the ROM enable jumper is present, 2, AEN is LOW (DMA not active), and 3 the P side matches the R side (P=R). Those three conditions are only met when the CPU is doing a memory request in the address region of the ROM.

Thanks and have a nice day!

Andrew Lynch
 
Personally I look forward to it, and I'm prepared to put my money where my mouth is. If it lets me use a 16-bit IDE drive on my 8-bit 8086 I'll be happy. It'll allow our vintage machines to continue fulfilling their purpose for a long time to come.





BG
 
The 8-Bit Controller

The 8-Bit Controller

Hi Guys,

Way back in August of last year I originated this thread. I'm overwhelmed by the response. I still haven't scored a 8-Bit IDE controller, so I'm your best fan! I did get my old Tandy 1000SX up and running with a 8-Bit Tecram SCSI controller /w a 8 mb SCSI drive. Only problem is the primative BIOS doesn't want to see it on boot. The work-around for that is to boot off the floppy.

If I can help defray some of the R&D costs, please let me know.

Tom D.
 
per said:
I see now that it will work.

However, what I understand is that the AEN line is to prevent I/O transfers durning DMA. Since therse uses the data lines but aren't mapped in memory, they will corrupt data if they output durning DMA. However, since ROM is in the memory map, it will be acessed like all other memory if and only when DMA passes it's adresses. I see no reason why the ROM somehow should output data when the adressing lines are pointing to some other place in memory.

So, the only way the ROM can affect DMA is if DMA tries to read or write it by purpose. This is why I made my comment.
Click to expand...

Hi! Thank you for making the comments and challenging the design. If its wrong, I'll fix it and your improvements are always welcome. I have a thick skin and short memory from years in engineering so I expect to have to answer technical questions impartially. If I can't then its a risk area and everyone deserves to know about it!

Regarding the 8 bit IDE project; at least AFAIK, Hargle is leading this merry band to an 8 bit IDE product release. He has already written some software and coordinated the help among various experts and volunteers. That is great! I applaud his leadership and will do what I can to support him.

If Hargle can get his crew at work to make a PCBs, then I encourage that 100% as well. Especially a limited run of PCBs for a low rate initial production test. My offer, if Hargle's PCB run falls through for some reason, is to also do a PCB but I don't think many people are going to like my terms. This is not my core interest and as a result I am extremely risk averse. Especially lacking a working hardware prototype, things can get real sporty, real quick like.

However, if I can provide some advice, technical help, or even just light a fire under someone's chair then I'll do my best. In the meantime, I congratulate you on your progress so far and wish you the best of success on your project.

I have a new PCB in the trace routing optimizer grinding away with the fixes I mentioned this afternoon. They are incorporated and the PCB is being fixed up. There is not enough time for a really optimized PCB but I can send you a semi-decent looking PCB layout and schematic tomorrow. However the PCB layout with traces and fill zones incorporated won't be ready until tomorrow.

Regardless, the PCB and schematic are in dire need of some in depth, ruthless scrutiny from experienced technical designers and other experts on this board. The more review you get the better chance of success you'll have. Be polite when requesting reviews and help because you'll be asking for skills that are in demand and their time is valuable.

Also, you'll need to run the final PCB design through the FreeRouting.net autorouter sufficiently long enough to eliminate as many of the vias and unneeded traces as possible. This is a very time consuming process to result in an optimal board. My DiskIO board required 3 MONTHS in the optimizer to get it down to a reasonable level. Of course, the FDC and IDE sections and several dual row headers drove its complexity sky high so that is a really bad case. Your PCB won't be that bad but it will still take days or weeks to fully optimize. I recommend you do that once the design, schematic, and PCB layout are finished.

Thanks and have a nice day!

Andrew Lynch

PS, there is an updated ZIP file in the same place as before.
 
Wasn't there a (or some) programs out there, way back, that let you do a real time circuit simulation?

I remember downloading one by accident once and played with it a bit before deleting it.

It allowed you to set up input conditions to see what your output would be. Problem is, I'll be damned if I can remember the name of the program, but, this circuit shouldn't be beyond its capabilities, IIRC.
 
Hi Richard! That's a great idea! If you or anyone can find a TTL circuit simulator which doesn't cost an arm and a leg I surely would be interested. I recall using PSPICE in college for analog and transistor circuits but haven't used anything like that recently.

The really sad part about this is building a wire-wrap prototype of this board would take like one evening to do. I am wire-wrapping the Zilog Peripherals board on my workbench right now for development and testing on the N8VEM project. I am using one of the N8VEM ECB prototyping boards and it is packed full of sockets (8 misc logic, the 4 Zilog chips, 3 MAX232s with caps, and a couple of configuration headers) and its going to be there for while I can see.

Assuming I had the parts (ISA prototyping board and the WW dual row connectors -- neither are an issue, I just don't have one at home since I haven't needed it) and the *space* (now that's an issue!) for a XT or AT set up, making one of boards would fairly easy. That's what really frustrates me! I have the rest of the stuff just sitting there ready to go but no *room* for another work area. Argh! Oh well!

Thanks and have a nice day!

Andrew Lynch
 
lynchaj said:
Regarding the 8 bit IDE project; at least AFAIK, Hargle is leading this merry band to an 8 bit IDE product release. He has already written some software and coordinated the help among various experts and volunteers. That is great! I applaud his leadership and will do what I can to support him.
Click to expand...
thank you for the kind words. i won't rest until i see this thing shipping as a finished product. For me, it's a mixture of wanting a board for myself, plus the challenge and opportunity to write some BIOS code and to just create something, plus wanting to make it all open source for the community, plus the fact that i'm too cheap to buy one off ebay. ;)

up. There is not enough time for a really optimized PCB but I can send you a semi-decent looking PCB layout and schematic tomorrow. However the PCB layout with traces and fill zones incorporated won't be ready until tomorrow.
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All I really need is the schematic. My guy here said that he will unfortunately just have to enter it in again into our toolset (I don't know what tools we use) but that shouldn't take too much time, and he's bored anyway. :)


In other news, I've started writing a flash program for the eeprom.
It looks really easy to work with, and it's super cool that it has a spare 64 bytes of storage outside the 8k block that I could use for custom options.
Since the eeprom 8k in size, and my BIOS code is only 1/2 that, I could create a boot utility that could allow you to set defaults for booting drive order, passwords, drive options or anything else we wanted to do, all stored in the eeprom itself. Fun!
 
Hi Hargle! As promised, I updated the zip file with all the latest prints and files. It is ready to go. I will keep the PCB in the trace optimizer on a low simmer as a backup in case things don't work out at your work.

It will be good to have a back up and it will be a while before I need that machine to process the Zilog Peripherals board I am presently building. The PCB is simple enough it may actually finish in a reasonable time!

I am excited about the project as well and look forward for PCB availability. Please put me down for a couple!

Thanks and have a nice day!

Andrew Lynch

PS, I checked this morning and the optimizer has reduced the PCB trace routing to 60 vias and like ~357 inches overall trace length. That's pretty good but I suspect it has a long ways to go yet. Has anyone gotten some more reviews of the schematic and/or design? Hargle, please ask your PCB designers to ensure the vias and trace routing are minimized to the extent possible/practical. It makes difference in performance and reliability of the circuit.
 
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Druid6900 said:
Wasn't there a (or some) programs out there, way back, that let you do a real time circuit simulation?

I remember downloading one by accident once and played with it a bit before deleting it.

It allowed you to set up input conditions to see what your output would be. Problem is, I'll be damned if I can remember the name of the program, but, this circuit shouldn't be beyond its capabilities, IIRC.
Click to expand...

Hi Richard! Thanks! Your comment rather started my brain to thinking and I found this project which just might be the item we're looking for.

I am back on the N8VEM project but does anyone want to give QUCS a try and see if they can simulate the IDE circuit? It may be possible but I have no idea if it works or not. Surely the schematic would have to be completely re-entered as it does not appear to support any import feature. Maybe I missed it though.

If someone is looking for a way to contribute to this project, here is your chance!

Thanks and have a nice day!

Andrew Lynch
 
Hi! My friend Dave pointed out that the R side of the 74LS688s should have pull up resistors and not left to float. Probably it would work with out them and the original schematics did not include them, however, it is good practice to bring an input signal to either HIGH or LOW and not leave it floating.

I have corrected my schematic and will rerun the PCB layout. The changes are minimal but important.

Thanks and have a nice day!

Andrew Lynch
 
I think I may have found something in the design:
CSEL on the 40 pin connector should be pulled to ground instead of VCC.

http://www.pcguide.com/ref/hdd/if/ide/confCS-c.html
"To use cable select, both devices on the channel are set to the "cable select" (CS) setting, usually by a special jumper. Then, a special cable is used. This cable is very similar in most respects to the regular IDE/ATA cable, except for the CSEL signal. CSEL is carried on wire #28 of the standard IDE/ATA cable, and is grounded at the host's connector (the one that attaches to the motherboard or controller). "

I think this is very minor though. Most of the rest of the schematic is goobledygook to me.

---

Looking at the board layout in kicad, I'm wondering how in the world I could ever hand wire a prototype of this thing. I'm thinking it very well may be worth a hundred bucks of my money to save me 100 hours of soldering and get a prototype board etched for me. Wow that's a lot of wires.
 
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hargle said:
I think I may have found something in the design:
CSEL on the 40 pin connector should be pulled to ground instead of VCC.

http://www.pcguide.com/ref/hdd/if/ide/confCS-c.html
"To use cable select, both devices on the channel are set to the "cable select" (CS) setting, usually by a special jumper. Then, a special cable is used. This cable is very similar in most respects to the regular IDE/ATA cable, except for the CSEL signal. CSEL is carried on wire #28 of the standard IDE/ATA cable, and is grounded at the host's connector (the one that attaches to the motherboard or controller). "

I think this is very minor though. Most of the rest of the schematic is goobledygook to me.

---

Looking at the board layout in kicad, I'm wondering how in the world I could ever hand wire a prototype of this thing. I'm thinking it very well may be worth a hundred bucks of my money to save me 100 hours of soldering and get a prototype board etched for me. Wow that's a lot of wires.
Click to expand...

Hi Hargle! Thanks! I appreciate your reviewing the schematics and searching for problems! That's how we make it better! Just keep digging and we'll get all the bugs out.

As for CSEL, that is an active high signal since there is no ! or ~ or / or * or - or other special character preceding the name. Active high means that the signal is asserted (do something!) when it reaches the TTL high state (2.0-5v). Pulling CSEL high is basically telling the IDE device that it is being selected and should respond to commands.

I implemented a circuit similar to this on my N8VEM Disk IO prototype board and it worked fine.

http://www.hanssummers.com/computers/cpcng/ide/

You'll notice it also pulls CSEL high with a 10K ohm resistor tied to VCC. At least my prototype worked with this as is. I am pretty confident the CSEL circuit is correct. However if there is more information or view points that could confirm or deny this I would much appreciate it.

However, one thing to note is Hans Summer's circuit and my own IDE controller for the N8VEM project are meant for the older parallel IDE devices. I believe the XT-IDE circuit is as well since it shows a similar heritage in the design. I'll bet they all stem from the same common root design although I don't know what that is. It is possible that newer IDE drives have implemented more recent standards which may or may not work with the IDE interface. I have only tested mine with a 1.2GB IDE which is rather *ahem* elderly.

In general, all related XT IDE technical topics, questions, suggestions, comments, etc should be considered as part of this project. I have no problem explaining my understanding and will gladly make corrections as needed. I would much rather face my problems here in the design phase then after the PCBs are manufactured.

As for wiring up this project, it would be an evening at most. Its not super simple but pretty close. There are about 10 chips and very few passive devices. Only one connector although it is a large one. If I had the ISA prototyping board I am sure I could do this in one evening for construction and another for schematic to wiring test wring out.

Don't sell yourself short! You can do this or could if you set your mind to it! Check this unit out! That's an IDE controller on the top half of the board and an FDC on the bottom. There are other pictures of the other side and there are another three or more "flying" chips (aka dead bugs) wired in backwards to the board because I ran out of space constructing the prototype. I can that that monstrosity to work (IDE and FDC), then you can make this one work!

Its not that hard! Anyone can do it! I think you'd find it is rewarding and a fun hobby too. I know I do. The danger with going direct to a PCB is there is no guarrantee that one PCB spin is all you need. At $100-$200 per hand, this gets to be an expensive game. One error may be serious enough to cause a PCB respin and then the old PCBs *can* be nearly worthless. Usually the problems are fixable with sufficient "cuts and jumpers" but those aren't much fun either and we all want to avoid them if possible.

So how is the rest of the project coming along? Keep those questions and comments coming! Read those datasheets and ask questions! You just might uncover the major "show stopper" bug that saves the project!

Thanks and have a nice day!

Andrew Lynch

PS, while doing a search for "74LS688 IO decoder" I came across this link which is in many ways similar to what we are doing here. There are a lot of ideas in it and is a good cross comparison of the IDE circuit.
 
lynchaj said:
I am pretty confident the CSEL circuit is correct. However if there is more information or view points that could confirm or deny this I would much appreciate it.
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I came across it by comparing the 40 pin connector against the schematic I had of a motherboard my group had produced. We've always pulled CSEL low in our designs (probably a dozen of them), and all of them have also worked just fine. Likely, it doesn't matter 1 iota which way it goes, as the drive itself is going to override it anyway!

Beyond that, i haven't really figured anything else out. Well, I think I figured out the decoding for the IO address decoding dipswitch, where it appears it can be configured anywhere from 3F0h down to 000 in 10h increments. That's an amazing amount of flexibility. (which also means I have to scan all those addresses to find the card!)

I'm currently looking through the 74ls138 datasheet to try and figure out how that is working to flip between the two 74ls573's. I understand the idea; just haven't quite gotten my mind around the logic+inverter+output selects and what makes 'em work. It's really interesting stuff though, but I don't feel i'm very qualified to review it the way it should be, and I'm certainly ignoring everything that has to do with voltage levels and the like. I'm relying on others to chime in and give it some eyes.

As for wiring up this project, it would be an evening at most.
If I had the ISA prototyping board I am sure I could do this in one evening for construction and another for schematic to wiring test wring out.
Click to expand...
I'll buy you 5 of them if you build me 1....

So how is the rest of the project coming along?
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the schematic is the only thing i'm working on. my coworker got slammed with stuff to do, so he can't review the schematics this week, and I haven't touched the option rom since I released it. I've got ideas bubbling in my head for it, but that's it.
 
I have just started to write a debugging tool that might be usefull in debugging the prototype board when it is done, see the attachement for a beta of this program.

What this program does is to print all possible "in ax,dx" or "in al,dx" to the screen in an organized manner, and it even gives you the ability to do either an "out dx,ax" or "out dx,al" with both ax and dx user-configureable. WARNING: playing around with random out's might be dangerous to your system. I'm NOT responsible if you fry anything in or outside your computer.

I will also implement a memory controll senter somewhat similar to this in the final release.
 

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Lynchaj wrote:
Hi Hargle! Thanks! I appreciate your reviewing the schematics and searching for problems! That's how we make it better! Just keep digging and we'll get all the bugs out.

As for CSEL, that is an active high signal since there is no ! or ~ or / or * or - or other special character preceding the name. Active high means that the signal is asserted (do something!) when it reaches the TTL high state (2.0-5v). Pulling CSEL high is basically telling the IDE device that it is being selected and should respond to commands.

I implemented a circuit similar to this on my N8VEM Disk IO prototype board and it worked fine.
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That's not quite my understanding of the CSEL signal; it's not "active high" (or low) because it selects master/slave (Low=master, High=slave) when the drives are set to CS and a special cable is used which only passes it to one drive, and as Hargle says it is usually set low permanently on the MB.

But if the drives are set to master/slave then it is irrelevant AFAIK, which is probably why it worked for you.
 
MikeS said:
Lynchaj wrote:
Hi Hargle! Thanks! I appreciate your reviewing the schematics and searching for problems! That's how we make it better! Just keep digging and we'll get all the bugs out.

As for CSEL, that is an active high signal since there is no ! or ~ or / or * or - or other special character preceding the name. Active high means that the signal is asserted (do something!) when it reaches the TTL high state (2.0-5v). Pulling CSEL high is basically telling the IDE device that it is being selected and should respond to commands.

I implemented a circuit similar to this on my N8VEM Disk IO prototype board and it worked fine.
-------------
That's not quite my understanding of the CSEL signal; it's not "active high" (or low) because it selects master/slave (Low=master, High=slave) when the drives are set to CS and a special cable is used which only passes it to one drive, and as Hargle says it is usually set low permanently on the MB.

But if the drives are set to master/slave then it is irrelevant AFAIK, which is probably why it worked for you.
Click to expand...

Hi Mike! Thanks! You are probably right on the CSEL. You'll notice that the circuit uses a 10K ohm pull up resistor tied between Vcc and CSEL. At least in theory, if the pin were shunted to ground the CSEL signal would be low. If it were left without a shunt (open) the pull up resistor would pull CSEL to high. In either case the CSEL signal is forced to a known state which is good. The real danger would be leaving CSEL floating in an indeterminate state in the "no man's land" where its neither high nor low or worse, oscillating.

As it is, leave it alone and CSEL will be HIGH. Use the shunt on the cable and it will be LOW.

That reminds me though, I need to check the specific configuration of the IDE harddrive I have connected to my N8VEM Disk IO prototype board to see what its settings are. I vaguely recall having to jostle around the cable and the jumpers to get the drive to recognise. Probably the CSEL is why. If that drive is set to SLAVE IDE then it makes perfect sense.

It may be worthwhile to put a jumper on the PCB for CSEL or just use jumper on the IDE cable.

Thanks and have a nice day!

Andrew Lynch
 
Hi! This is a copy of a message from the N8VEM mailing list on the Disk IO board. The Disk IO board is different from the XT-IDE controller but it does have some similarity and may be useful in helping narrow the drive compatibility/CSEL issues that will no doubt arrise.

Thanks and have a nice day!

Andrew Lynch

Hi All! Well the good news is that I finished building my Disk IO board. It looks fine but I haven’t tested it yet as I don’t want to start that until I get the Zilog Peripherals completed and off the bench or I’ll never finish it. There are some photos in the Disk IO directory on the wiki.

I did want to let the builders know that if they are building a Disk IO board that there are two halves to the design. The IDE section can function separately from the FDC, at least it did with the prototype for quite a while. There is minimal sharing of circuits between the two halves but you’ll need to review the schematic if you are interested in a partial build to ensure the parts you need are present.

Probably the best approach for a build and test of the Disk IO board is to start with the IDE section. It quite a simple design and pretty easy to debug. You can access the IDE registers directly from the RAM monitor and I think they are in the $2x range. There are descriptions online of the IDE interface and there is information in the IDE test program and formatting utility as well as the CBIOS.

Also I used the IDE to interface to a single IDE device so it is entirely likely the software will need to be modified to work with other devices. I used a Seagate ST51270A drive with NONE of the configuration jumpers set. That puts the drive in “single drive mode”. I also used a 40 pin IDE cable with the motherboard connector on the controller and the far end connector on the hard drive.

Hopefully this helps the builders get their own Disk IO board up and running. You could do a full board build all at once but I recommend getting the IDE section working first. Of course, please post your results and lots of photos for the wiki and tell us all about your experiences on the mailing list.

http://www.codemicro.com/support/disc/ata/st51270a.html

http://stason.org/TULARC/pc/hard-dr...70A-MEDA-1270SL-1282MB-3-5-SSL-ATA2-FAST.html

http://n8vem-sbc.pbwiki.com/f/IMG_8632.JPG

http://n8vem-sbc.pbwiki.com/f/IMG_8631.JPG

http://n8vem-sbc.pbwiki.com/f/IMG_8630.JPG

Thanks and have a nice day!

Andrew Lynch
 
Let the prototyping begin!

Last week friday I went out to a local electronics store and was able to pick up all the parts (I hope) required to build it, and on saturday the ISA prototype boards showed up. we're ready to roll!!

I bought 2 sets of everything, and will be sending 1 set to andrew to build, while I (attempt to) build the other one. Hopefully in a few days we can get something plugged in and tested. Unfortunately, I have a bunch of things in my real life schedule that will likely interfere with my building process.

------

My HW guy here mentioned that we should decouple all of the ICs by adding a 0.10uF caps across the power and ground pins. Does that make sense?
 
hargle said:
My HW guy here mentioned that we should decouple all of the ICs by adding a 0.10uF caps across the power and ground pins. Does that make sense?
Click to expand...

That's problably for removing noise. you don't want all of your latches/flip-flops/etc. to be reset in the middle of an operation ;) .
 
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