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Ac lo, dc lo

Activmaker

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Hi,

In documentation we find explanations about power up and down sequences. The documentation talks about "AC in spec and DC in spec" . I Would like to know what "spec" means exactly ..For AC it is frequency , voltage range? . I think that for DC it is only voltage range but not sure...Where can I find this kind of informations, I would like to simulate these signals .
Thanks in advance.
 

billdeg

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I created a summary PDF of the mainframe troubleshooting guide by removing all but the pages I needed to support my PDP 11/40.
http://vintagecomputer.net/digital/PDP-11_Mainframe_Troubleshooting_Guide_Dec76.pdf

Basically AC LO and DC LO are measured from test points on the wirewrap side of the CPU backplane, or other spots depending on the system you're working on. Here is a pic from my PDP 11/40.
http://vintagecomputer.net/digital/pdp11-40/PDP11-40_backplane_DC-input.jpg

The troubleshooting guide will tell you what the voltages should be. The system will bring DC or AC LO down if something is detected to be wrong. The values of at least 3.x volts are typical of a "good" AC LO or DC LO. In the case of a h742a power supply attached to a PDP 11/40 system I think it'd be more like 4.8v. AC LO and DC LO I think should measure very close to each other, if one is a lot less than the other there is a problem. BUT your system may vary.

More
http://vintagecomputer.net/browse_thread.cfm?id=178

b
 
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Activmaker

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Thanks a lot for the PDF, really interesting. But ,my question was not clear, I am talking about the electrical part that make AC or DC LO asserted. When you say "The system will bring DC or AC LO down if something is detected to be wrong". What do you call "something to be wrong" ? I suppose that there is a measure inside the power supply that compare the output voltage and a reference value , if output voltage is below reference , then DC LO is asserted . I would like to know the reason (and caracteristics) that can cause DC LO or AC LO asserted.
 

Bitly

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Hi,

In documentation we find explanations about power up and down sequences. The documentation talks about "AC in spec and DC in spec" . I Would like to know what "spec" means exactly ..For AC it is frequency , voltage range? . I think that for DC it is only voltage range but not sure...Where can I find this kind of informations, I would like to simulate these signals .
Thanks in advance.

I doubt the AC frequency would be measured, since it isn't meaningful to operation (except perhaps to the clock). Linear power supplies attach line voltage to one side of a transformer, take the stepped-down output from the transformer and feed it to a bridge rectifier and (large) electrolytic cap to clean up the ripple. This is *probably* where the voltage for ACLO is measured. It could also be measured at line voltage, but high voltage AC comparators are difficult to build and fiddly to operate.

The ACLO threshold is probably an input referred ~85VAC, depending on how much margin there is between the output of the rectifier and the dropout voltage of the regulator for line voltage.

DCLO would just be comparators off one or more of the voltage rails probably set to -10% of nominal.

CW
 

billdeg

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With all due respect, Bitly ... in the context of the question your response is off the mark to the question. AC LO and DC LO are Digital Equipment Corp-specific terms that have nothing directly to do with the AC DC voltages in a power supply. The abridged manual link I supplied has more detail. Why they called these test points AC LO and DC LO is a different story. I am not a DEC expert btw, but enough at least to have repaired a number of DEC UNIBUS systems and learned a lot that way. There are others here who really know there stuff and who can get into the AC LO DC LO purpose specific to a case. If you read the manuals for a CPU card (for example) they're designed to detect certain conditions and force a "DC LO" or "AC LO" response on the UNIBUS backplane, used to signal the source of the problem.

b
 

billdeg

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Thanks a lot for the PDF, really interesting. But ,my question was not clear, I am talking about the electrical part that make AC or DC LO asserted. When you say "The system will bring DC or AC LO down if something is detected to be wrong". What do you call "something to be wrong" ? I suppose that there is a measure inside the power supply that compare the output voltage and a reference value , if output voltage is below reference , then DC LO is asserted . I would like to know the reason (and caracteristics) that can cause DC LO or AC LO asserted.

That's just it, it's NOT used to indicate an electrical failure. These are labels *called* AC LO and DC LO, they're not the actual AC nor DC measurements at all. Capiche? You read AC LO and DC LO off the backplane, not the power supply. They're used as indicator values for troubleshooting. Confusing yes, because there are also points where one can read the exact +/-5V (for example) right next to the AC LO DC LO.

When the CPU initiates it carries out a series of steps electrically/logically. Those diagrams in the troubleshooting charts outline the various failure points that cause among other things the system to drop the AC LO or DC LO. Each controller card has a manual. It's case by case; a chip being bad, a failure in the power supply, a cable plugged in the wrong way...

Remove all non essential cards. Power up the system. Measure your voltages off the backplane including AC and DC LO, use the troubleshooting manual to narrow down what the source of the problem is. Get the manual for the component that the troubleshooting guide suggests is the point of failure. IN there, that manual will tell you which thing when it fails causes AC LO or DC LO to fall lower than (often extactly by 50%) "quiescent" the term DEC uses for everything is ok.

So, what kind of system are we talking about here? Let's see if we can use your case as an example of how to use AC LO and DC LO to troubleshoot.
 

MattisLind

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This AC LO and DC LO is nothing complicated, really. They are signals generated by the PSU (or PSUs if you have several) normally. Possibly any one can generate these signals since they are active low wire-ored. But I have only seen these coming from PSUs. Not IO boards or similar

It has nothing to do with the frequency. It just measures certain voltages inside the PSU.

This is the spec (from the 11/05 manual, but I assume it is the same with any PDP-11)

f6VEmitl.png


Well it says High state goes to high. Has to be a typo. Should read Low state goes to High

ShOW2yrl.png


So what Bitly wrote is probably quite reasonable.

And here is the description:

6lugCpjl.png


And the actual circuit in the 11/05 PSU:

UOpl23tl.png


The reason for these signals is obviously to make sure that all PSUs have the correct output and then let the processor out of RESET.

Here is the description for a PDP-11/05 deals with the power fail and auto-restart using these signals.

sEv3gvfl.png

9qqPm0Yl.png

RefuCBUl.png
 

billdeg

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I agree that the origin of the signal is the PSU, but I have found that certain controllers will halve the original value electronically and change the DC LO of AC LO signal in a predictable way to force the system out of quiescence state. That's what I meant. Yes you may have to simply fix the power supply, but it's not always true that the resolution to the problem of a AC LO / DC LO issue is the power supply.
 

MattisLind

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I agree that the origin of the signal is the PSU, but I have found that certain controllers will halve the original value electronically and change the DC LO of AC LO signal in a predictable way to force the system out of quiescence state. That's what I meant. Yes you may have to simply fix the power supply, but it's not always true that the resolution to the problem of a AC LO / DC LO issue is the power supply.

You need to be a bit more elaborate here. What do you mean by "halve the original value electronically"? AC LO and DC LO are logical open collector signals, active low. They are either low or high.

It would be interesting if you could give examples on controllers that output AC LO / DC LO.
 

billdeg

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I thought you'd have come across this effect in your travels, too. In my 11/40 in particular there is a CPU card in the set that cuts the signal in half seemingly by design. When I was knee deep in the thing I would have had it memorized what/where but it has been a year and I'd have to look up the specifics. I am at work but it's in the 11/40 doc somewhere. Note that I have also had issues with my h742a power supply board that caused DC LO to fail "directly".

I am working on the clock at the moment, but if it's really important I can try to find which 11/40 CPU card effects or contributes to the value of DC LO or AC LO.

I honestly thought all DEC machines manipulated DC LO and AC LO to indicate there was a problem with selected components, but I am open to being corrected, I just wanted to help the OP'er with my experience.

b
 
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daver2

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On my 11/45 the AC LO and DC LO signals (note the plurality) are generated purely by the power supply units themselves and (as has been previously stated) drive the PDP-11/45 into taking immediate action (such as saving the registers into non-volatile storage) in response to the impending power failure.

Within each of the regulator racks is a separate power control board. It is this unit that produces the AC LO and DC LO signals. Because there are two separate power supply racks - there are two sets of separate signals. Each power control board can produce separate outputs. The AC input voltage (from the step down transformer) is rectified and a very low valued electrolytic capacitor (20 uF) provides a degree of smothing. The voltage of this rail is then compared to a set of presets (I can't remember the exact voltage threshold) and it is this that is used to drive the AC LO and DC LO signals (open collector).

The switched mode regulators themselves are separe entities fed from separate low-voltage ac windings off the transformer. These regulators are not monitored. Hence, a switched mode regulator can fail - but the DC LO signal never operates - i.e. the AC LO and DC LO signals indicate impending incoming manins power failure and not necessarily a fault within the PDP-11.

Regards,

Dave
 

billdeg

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basically I must have discovered something that was just a coincidence to cause the DC LO value to halve, I believe there are much better answers than mine the followed what I wrote, please consider what I wrote to be observations and not facts.
 

Activmaker

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For people who want more about AC LO and DC LO I found in EK-BA11L-TM-001_Oct77.pdf the explanation about H777 Power supply. (Figure 3.25 on page 3.43) Details are given and schematics are explained. But nothing about component values , I will search H777 Schematics.
 
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