As far as polling the MC6850 that's fine for lower speed data communications, but the MC6850 has a RTS (output) and CTS (input) signal pins for the serial ports' signals, so use them instead of polling. It is easy to build logic to detect when a "fresh" data byte is available without polling.
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A short not on the MC6850 ACIA chip (for other readers how are not too familiar with it.) Just some basic crap about it.
The Mc6850 ACIA does have signals pins for: /CTS and /RTS, /DCD, Rx data, TC data, Rx clk input, Tx clk input.
Enable input can be used as a Data Strobe and Clock latch strobe. On some systems the Address bus is also active when this signal is active.
/IRO output can be combined with CTS and RTS signals to emulate wither the Transmit channel side or Receive Channel side has a Int.
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On some systems the Mc6850 CS signal is inverter to RS232C leaves and is combined with /RTS to form the /DTR signal.
The RI (Ring indicated) is tied to the DCD signal and sometimes also to the CTS signal.
As far as RI, DTR and DSR these signals could always be routed to an unused PIA port for enhanced serial port status.
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3 CS signal lines plus 1 RS signal pin is used to select between the Data register and the Status control registers. The RD//WR signal controls the Bus direction.
the maximum data rate early versions support is 500K Bits per second (without overclocking caching)
the number of data bits is 8 bit and the rest of the information someone could always look up (if they wish to).
The standard MC6850 from 1978 will support up to 500K bps - Confirmed from my 1978 "The Complete Motorola Microprocessor Data Library" book.
Other data I have confirmed from the 3Rd party Advance Applications notes for the MC6850 ACIA.
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Tristate or no tristate on the 6502 microprocessors, yes, some 3RD parity and newer versions had it built it.
But with the clock signals on the 6502 microprocessors that do not support it
, you can simulate it by using external logic and decoding the full clock cycles.
The 6502 Microprocessor
As far as being MotorolaMC6800 bus compatible, with the full decoding of all the 6502 Clock cycle signals (, yes input and outputs ones) you can fully simulate
all of the MC6800 bus signals. They can be simulated in the 6502 clock signals, but you must externally decode them.
Bus Available (BA), Data Bus Enable (DBE) also known as 02 clk or E signal are encoded on the microprocessors clock pins.
External HALT(Stop) and it's acknowledged signal is usually done by external logic circuity.
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Technically the 6502 has Three state control status emulation/simulation encoded on its multiphase clock cycle signals pins, but most boards don't interment it and on most simple hardware it is not used anyways. Real Three state control is available on some advances 3Rd party clones, so some extra external logic is not needed.
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Yes, the original 6502 has no built-in mechanism to tri-state its address bus, but you can emulate it with a small circuit built with a flip-flop.
You can temporary pause (or wipe the microprocessors memory) the 6502 microprocessors by external manipulation of its clock input signal.
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DMA or IDMA emulation with the 6502 microprocessors
You can Nore Gate the 6502 microprocessor o2Clk out pin 39 with the 0O clock signal on Pin 37 to generate a S01 Clock signal is used for compatible VPMA Access and NOVPMA access signals.
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You can pull the microprocessor 01 clock high just after a 02 clock cycle to suspend the microprocessor for 4 system 01 clock cycles before destroying data within the microprocessor. This hidden TSC time then can be used in a short DMA application. With a custom burst control circuit, you can transfer 8 bytes in this time slot if the memory can support it. (Limited by the bandwidth of memory logic). This is mostly undocumented 6502 data.
The Sync signal line with the use of the o1 clock signal and the RDY signal can be used to single step the microprocessors instructions.
The IRQ signal is sampled during a 02 clock operation, if the microprocessor is set for interrupts it would start on the next 01 Clock cycle (on some variants its timing is somewhat different).
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Note: Clk=Clock
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The 6502 02 clock signal is the same as E signal on the MC6821 PIA
At least Commodore (MOS Technologies) with the 6510 built in the tristate logics removing some external logic that helps reduce the microprocessor customer products cost.